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Message-ID: <alpine.DEB.1.10.0902111341170.15438@gandalf.stny.rr.com>
Date: Wed, 11 Feb 2009 13:42:32 -0500 (EST)
From: Steven Rostedt <rostedt@...dmis.org>
To: "Luck, Tony" <tony.luck@...el.com>
cc: Ingo Molnar <mingo@...e.hu>, Mike Travis <travis@....com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Thomas Gleixner <tglx@...utronix.de>,
Peter Zijlstra <peterz@...radead.org>,
Arnaldo Carvalho de Melo <acme@...hat.com>,
Frederic Weisbecker <fweisbec@...il.com>,
"isimatu.yasuaki@...fujitsu.com" <isimatu.yasuaki@...fujitsu.com>,
"kaneshige.kenji@...fujitsu.com" <kaneshige.kenji@...fujitsu.com>
Subject: RE: [PATCH 0/8] git pull request for tip/tracing/core
On Wed, 11 Feb 2009, Luck, Tony wrote:
> > The bits in question is really the number of possible nested interrupts
> > that can happen. We take the paranoid approach that we can have a max
> > nesting of NR_IRQS. Perhaps this can be changed, and just do a max of
> > 1<<10 nesting? And have a big warn on if it happens to be bigger, or fall
> > to another counter if it is bigger.
> >
> > 1000 nested IRQs seems a bit extreme :-/
>
> Ah, I see. Then the answer is very different. The number of nested
> interrupts possible on a cpu is limited by the number of priority
> classes for interrupts (See Table 5-8 on page 2:112 of the Itanium
> software developers manual). Effectively the max nesting depth is
> 16.
>
> 1000 nested interrupts would be certain to run us out of stack.
Ingo,
Do you think this is a good assumption to make, that no arch will have
over 1<<10 nested interrupts. We can add a WARN_ON if it happens. Then we
can make all archs have a 10 bit offset. Smaller may also be sufficient.
-- Steve
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