linux-kernel - [PATCH] [6/9] x86: CMCI: Define MSR names and fields for new CMCI registers

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Message-Id: <20090212124935.5794F3E666E@basil.firstfloor.org>
Date:	Thu, 12 Feb 2009 13:49:35 +0100 (CET)
From:	Andi Kleen <andi@...stfloor.org>
To:	akpm@...ux-foundation.org, mingo@...e.hu, tglx@...utronix.de,
	hpa@...or.com, linux-kernel@...r.kernel.org
Subject: [PATCH] [6/9] x86: CMCI: Define MSR names and fields for new CMCI registers


CMCI means support for raising an interrupt on a corrected machine
check event instead of having to poll for it. It's a new feature in 
Intel Nehalem CPUs available on some machine check banks.

For details see the IA32 SDM Vol3a 14.5

Define the registers for it as a preparation for further patches.

Signed-off-by: Andi Kleen <ak@...ux.intel.com>

---
 arch/x86/include/asm/apicdef.h   |    1 +
 arch/x86/include/asm/mce.h       |    2 ++
 arch/x86/include/asm/msr-index.h |    5 +++++
 3 files changed, 8 insertions(+)

Index: linux/arch/x86/include/asm/msr-index.h
===================================================================
--- linux.orig/arch/x86/include/asm/msr-index.h	2009-02-12 11:30:45.000000000 +0100
+++ linux/arch/x86/include/asm/msr-index.h	2009-02-12 11:30:51.000000000 +0100
@@ -77,6 +77,11 @@
 #define MSR_IA32_MC0_ADDR		0x00000402
 #define MSR_IA32_MC0_MISC		0x00000403
 
+/* These are consecutive and not in the normal 4er MCE bank block */
+#define MSR_IA32_MC0_CTL2		0x00000280
+#define CMCI_EN			(1ULL << 30)
+#define CMCI_THRESHOLD_MASK		0xffffULL
+
 #define MSR_P6_PERFCTR0			0x000000c1
 #define MSR_P6_PERFCTR1			0x000000c2
 #define MSR_P6_EVNTSEL0			0x00000186
Index: linux/arch/x86/include/asm/mce.h
===================================================================
--- linux.orig/arch/x86/include/asm/mce.h	2009-02-12 11:30:51.000000000 +0100
+++ linux/arch/x86/include/asm/mce.h	2009-02-12 12:10:17.000000000 +0100
@@ -11,6 +11,8 @@
  */
 
 #define MCG_CTL_P	 (1UL<<8)   /* MCG_CAP register available */
+#define MCG_EXT_P	 (1ULL<<9)   /* Extended registers available */
+#define MCG_CMCI_P	 (1ULL<<10)  /* CMCI supported */
 
 #define MCG_STATUS_RIPV  (1UL<<0)   /* restart ip valid */
 #define MCG_STATUS_EIPV  (1UL<<1)   /* ip points to correct instruction */
Index: linux/arch/x86/include/asm/apicdef.h
===================================================================
--- linux.orig/arch/x86/include/asm/apicdef.h	2009-02-12 11:30:45.000000000 +0100
+++ linux/arch/x86/include/asm/apicdef.h	2009-02-12 11:30:51.000000000 +0100
@@ -53,6 +53,7 @@
 #define		APIC_ESR_SENDILL	0x00020
 #define		APIC_ESR_RECVILL	0x00040
 #define		APIC_ESR_ILLREGA	0x00080
+#define 	APIC_LVTCMCI	0x2f0
 #define	APIC_ICR	0x300
 #define		APIC_DEST_SELF		0x40000
 #define		APIC_DEST_ALLINC	0x80000
--
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