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Message-ID: <20090224185200.GA23109@elte.hu>
Date:	Tue, 24 Feb 2009 19:52:00 +0100
From:	Ingo Molnar <mingo@...e.hu>
To:	Paul Mackerras <paulus@...ba.org>
Cc:	linux-kernel@...r.kernel.org
Subject: Re: [PATCH] perfcounters/powerpc: Make exclude_kernel bit work on
	Apple G5 processors


* Paul Mackerras <paulus@...ba.org> wrote:

> Currently, setting hw_event.exclude_kernel does nothing on the PPC970
> variants used in Apple G5 machines, because they have the HV (hypervisor)
> bit in the MSR forced to 1, so as far as the PMU is concerned, the
> kernel runs in hypervisor mode.  Thus we have to use the MMCR0_FCHV
> (freeze counters in hypervisor mode) bit rather than the MMCR0_FCS
> (freeze counters in supervisor mode) bit.
> 
> This checks the MSR.HV bit at startup, and if it is set, we set the
> freeze_counters_kernel variable to MMCR0_FCHV (it was initialized to
> MMCR0_FCS).  We then use that whenever we need to exclude kernel events.
> 
> Signed-off-by: Paul Mackerras <paulus@...ba.org>
> ---
> Ingo, please pull this from my perfcounters.git tree master branch at:
> 
> git://git.kernel.org/pub/scm/linux/kernel/git/paulus/perfcounters.git master
> 
>  arch/powerpc/kernel/perf_counter.c |   23 ++++++++++++++++++-----
>  1 files changed, 18 insertions(+), 5 deletions(-)

pulled, thanks Paul!

	Ingo
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