linux-kernel - Re: [PATCH 17/18] Blackfin Serial Driver: Fix bug - Enable hardware based CTS and RTS for bf548.

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Message-Id: <20090306143831.2b8c6c83.akpm@linux-foundation.org>
Date:	Fri, 6 Mar 2009 14:38:31 -0800
From:	Andrew Morton <akpm@...ux-foundation.org>
To:	Bryan Wu <cooloney@...nel.org>
Cc:	alan@...rguk.ukuu.org.uk, linux-kernel@...r.kernel.org,
	sonic.zhang@...log.com, cooloney@...nel.org
Subject: Re: [PATCH 17/18] Blackfin Serial Driver: Fix bug - Enable hardware
 based CTS and RTS for bf548.

On Fri,  6 Mar 2009 14:42:59 +0800
Bryan Wu <cooloney@...nel.org> wrote:

> From: Sonic Zhang <sonic.zhang@...log.com>
> 
> Both software emulated and hardware based CTS and RTS are enabled in
> serial driver.
> 
> The CTS RTS PIN connection on BF548 UART port is defined as a modem
> device not as a host device. In order to test it under Linux, please
> nake a cross UART cable to exchange CTS and RTS signal.
> 
> Signed-off-by: Sonic Zhang <sonic.zhang@...log.com>
> Signed-off-by: Bryan Wu <cooloney@...nel.org>
> ---
>  .../mach-bf518/include/mach/bfin_serial_5xx.h      |   10 +-
>  .../mach-bf527/include/mach/bfin_serial_5xx.h      |   10 +-
>  .../mach-bf533/include/mach/bfin_serial_5xx.h      |    9 +-
>  .../mach-bf537/include/mach/bfin_serial_5xx.h      |   10 +-
>  .../mach-bf538/include/mach/bfin_serial_5xx.h      |   10 +-
>  .../mach-bf548/include/mach/bfin_serial_5xx.h      |   72 ++++-----
>  .../mach-bf561/include/mach/bfin_serial_5xx.h      |    9 +-
>  drivers/serial/Kconfig                             |   26 +++-
>  drivers/serial/bfin_5xx.c                          |  169 ++++++++++++++------
>  9 files changed, 209 insertions(+), 116 deletions(-)

This is a huge patch for us to be merging into -rc7.

> --- a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
> +++ b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
> @@ -53,9 +53,9 @@
>  #define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
>  #define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
>  
> -#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
> -#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
> -#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
> +#define UART_GET_CTS(x) (!gpio_get_value(x->cts_pin))
> +#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
> +#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
>  #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
>  #define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
>  
> @@ -74,6 +74,7 @@
>  struct bfin_serial_port {
>          struct uart_port        port;
>          unsigned int            old_status;
> +	int			status_irq;
>  	unsigned int lsr;

whitepace bustage in here.
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