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Message-Id: <1237029843-28076-1-git-send-email-sebastian@breakpoint.cc>
Date: Sat, 14 Mar 2009 12:24:01 +0100
From: Sebastian Andrzej Siewior <sebastian@...akpoint.cc>
To: linux-crypto@...r.kernel.org
Cc: tglx@...utronix.de, mingo@...hat.com, hpa@...or.com,
linux-kernel@...r.kernel.org, herbert@...dor.apana.org.au,
mail@...iasvolk.de
Subject: enable padlock on x86_64
To enable the padlock unit, two msr bits have to flipped. This is allready
done in the 32bit path and is missing in the other. Instead of copy paste
the code, I merged the 64bit part into the 32bit part. The things that
changed during the merge:
- the fixups from x86_64 (family 6, model >= 15) were not present in 32bit
path but are now. They might be usefull if this CPU is booted in 32bit
mode.
- the fixups which are executed via ->c_early_init() are now executed
again via ->c_init(). This was done in the 64bit path and without this I
lost the constant_tsc flag. However, tsc is not useable due to
| [ 2.023006] Marking TSC unstable due to TSC halts in idle
| [ 2.500082] Clocksource tsc unstable (delta = -326436711 ns)
The two patches are against the current tip tree. A version of patch 1
against current -rc8 is available at [0].
[0] http://download.breakpoint.cc/0001-x86-centaur-merge-32-64-bit-version.patch
Sebastian
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