| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <49CB4677.9010403@linux.intel.com> Date: Thu, 26 Mar 2009 10:10:15 +0100 From: Andi Kleen <ak@...ux.intel.com> To: Hidetoshi Seto <seto.hidetoshi@...fujitsu.com> CC: linux-kernel@...r.kernel.org, Ingo Molnar <mingo@...e.hu> Subject: Re: [PATCH -tip 1/3] x86, mce: Add mce_threshold option for intel cmci Hidetoshi Seto wrote: > This patch adds a kernel parameter "mce_threshold=n" to enable us > to change the default threshold for CMCI(Corrected Machine Check > Interrupt) that recent Intel processor supports. I intentionally didn't implement this because it seemed not needed. Any threshold in the actual error reporting should be implemented in the user space processing backend, but not in the CPU, because they typically need to be more fine grained than just per bank, and the CPU cannot do that. The only potential reason for implementing this threshold at the CPU level is if someone is concerned about CPU consumption during error storms. But then the threshold should be dynamically adjusted based on the current rate, otherwise it doesn't help. But I didn't do this so far because I didn't want to overengineer and in general if you have a error storm you're likely soon dead anyways. Also even if this was implemented a boot option would seem like the wrong interface compared to sysfs. Can you please describe your rationale for this more clearly? -Andi -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Powered by blists - more mailing lists