linux-kernel - Re: [PATCH] x86: cacheinfo: complete L2/L3 Cache and TLB associativity field definitions

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Message-ID: <20090403105832.GB6466@alberich.amd.com>
Date:	Fri, 3 Apr 2009 12:58:32 +0200
From:	Andreas Herrmann <andreas.herrmann3@....com>
To:	Ingo Molnar <mingo@...e.hu>
CC:	Mark Langsdorf <mark.langsdorf@....com>,
	"H. Peter Anvin" <hpa@...or.com>, Ingo Molnar <mingo@...hat.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH] x86: cacheinfo: complete L2/L3 Cache and TLB
	associativity field definitions

On Thu, Apr 02, 2009 at 12:30:08PM +0200, Ingo Molnar wrote:
> 
> * Andreas Herrmann <andreas.herrmann3@....com> wrote:
> 
> > Impact: complete cache information for AMD CPUs
> > 
> > See "CPUID Specification" (AMD Publication #: 25481, Rev. 2.28, April 2008)
> > 
> > Signed-off-by: Andreas Herrmann <andreas.herrmann3@....com>
> > ---
> >  arch/x86/kernel/cpu/intel_cacheinfo.c |   16 ++++++++++++----
> >  1 files changed, 12 insertions(+), 4 deletions(-)
> > 
> > Please apply.
> 
> Hm, the x86/cpu topic is marked broken and blocked by another AMD 
> patch from Mark Langsdorf:
> 
>  45ca863: x86, cpu: conform L3 Cache Index Disable to Linux standards

Oops, wasn't aware that you had applied this patch and I couldn't find
it in tip/master. Now I know why.

The code seems broken. Defining k8_northbridges in a header file is the
wrong thing to do. I'll look at it.


Andreas

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