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Message-ID: <20090409134710.GA8026@alberich.amd.com>
Date: Thu, 9 Apr 2009 15:47:10 +0200
From: Andreas Herrmann <andreas.herrmann3@....com>
To: Ingo Molnar <mingo@...e.hu>
CC: Mark Langsdorf <mark.langsdorf@....com>,
"H. Peter Anvin" <hpa@...or.com>, Ingo Molnar <mingo@...hat.com>,
Thomas Gleixner <tglx@...utronix.de>,
linux-kernel@...r.kernel.org
Subject: [PATCH v2] x86: cacheinfo: complete L2/L3 Cache and TLB
associativity field definitions
See "CPUID Specification" (AMD Publication #: 25481, Rev. 2.28, April 2008)
Signed-off-by: Andreas Herrmann <andreas.herrmann3@....com>
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 16 ++++++++++++----
1 files changed, 12 insertions(+), 4 deletions(-)
This patch applies on top of the changes sent with
[PATCH 0/8] x86: cacheinfo: cache_disable fixes/cleanup
Please apply.
Thanks,
Andreas
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 47e4fb4..3329347 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -200,10 +200,17 @@ union l3_cache {
};
static const unsigned short __cpuinitconst assocs[] = {
- [1] = 1, [2] = 2, [4] = 4, [6] = 8,
- [8] = 16, [0xa] = 32, [0xb] = 48,
+ [1] = 1,
+ [2] = 2,
+ [4] = 4,
+ [6] = 8,
+ [8] = 16,
+ [0xa] = 32,
+ [0xb] = 48,
[0xc] = 64,
- [0xf] = 0xffff // ??
+ [0xd] = 96,
+ [0xe] = 128,
+ [0xf] = 0xffff // fully associative - no way to show this currently
};
static const unsigned char __cpuinitconst levels[] = { 1, 1, 2, 3 };
@@ -264,7 +271,8 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
eax->split.type = types[leaf];
eax->split.level = levels[leaf];
if (leaf == 3)
- eax->split.num_threads_sharing = current_cpu_data.x86_max_cores - 1;
+ eax->split.num_threads_sharing =
+ current_cpu_data.x86_max_cores - 1;
else
eax->split.num_threads_sharing = 0;
eax->split.num_cores_on_die = current_cpu_data.x86_max_cores - 1;
--
1.6.2
--
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