[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20090423131941.GA11261@Krystal>
Date: Thu, 23 Apr 2009 09:19:42 -0400
From: Mathieu Desnoyers <mathieu.desnoyers@...ymtl.ca>
To: Ingo Molnar <mingo@...e.hu>
Cc: Alan Cox <alan@...rguk.ukuu.org.uk>, akpm@...ux-foundation.org,
linux-kernel@...r.kernel.org, mark.langsdorf@....com,
arekm@...en.pl, "H. Peter Anvin" <hpa@...or.com>,
Andi Kleen <andi@...stfloor.org>, Avi Kivity <avi@...ranet.com>
Subject: Re: [patch 2/2] x86 amd fix cmpxchg read acquire barrier
* Ingo Molnar (mingo@...e.hu) wrote:
>
> * Mathieu Desnoyers <mathieu.desnoyers@...ymtl.ca> wrote:
>
> > " // Opteron Rev E has a bug in which on very rare occasions a locked
> > // instruction doesn't act as a read-acquire barrier if followed by a
> > // non-locked read-modify-write instruction. Rev F has this bug in
> > // pre-release versions, but not in versions released to customers,
> > // so we test only for Rev E, which is family 15, model 32..63 inclusive.
>
> Dunno. The fix looks a bit intrusive (emits a NOP even on good
> CPUs). Also, the text above says "not in versions released to
> customers".
>
> So unless there's an official erratum or reports in the field (not
> from early prototype systems shipped to developers) i'd not rush to
> apply it, just yet.
>
Actually, Operon Rev E has this bug in the field (family 15, model
32..64). Rev F only had the bug in pre-releases.
But yes, it's bad that it drags so many code additions to something as
critical as cmpxchg. I start to think it might be better to just
disallow bringing up more than one CPU on these machines.
Mathieu
> Ingo
--
Mathieu Desnoyers
OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F BA06 3F25 A8FE 3BAE 9A68
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Powered by blists - more mailing lists