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Message-ID: <20090424092533.GA4720@codecarver.research.nokia.com>
Date: Fri, 24 Apr 2009 12:25:33 +0300
From: "Peter 'p2' De Schrijver" <peter.de-schrijver@...ia.com>
To: ext David Brownell <david-b@...bell.net>
Cc: lkml <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] TWL4030: add function to send PB messages
> > @@ -81,6 +82,69 @@ twl4030reg_write(struct twlreg_info *info, unsigned offset, u8 value)
> > value, info->base + offset);
> > }
> >
> > +static int twl4030_wait_pb_ready(void)
> > +{
> > +
> > + u8 pb_status;
> > + int status, timeout = 10;
> > +
> > + do {
> > + status = twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER,
> > + &pb_status, 0x14);
> > + if (status < 0)
> > + return status;
> > +
>
> Worth a comment that PB_CFG.BIT(0) == PB_I2C_BUSY ... true if there's
> a word queued for the power bus, but not yet sent. And that we assume
> no other I2C master is sending such events...
>
The multi master situation seems inherently racy to me anyway as you
need to write 2 bytes to 2 different registers to send 1 message. Or is there
a way to keep mastership of the bus between transactions ?
> > + /* Enable I2C access to powerbus */
> > + status = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER,
> > + pb_state | (1<<1), 0x14);
> > + if (status < 0)
> > + return status;
> > +
> > + status = twl4030_wait_pb_ready();
>
> I'd probably combine wait_pb_ready() with this; not that
> this is wrong, but you should only need to set BIT(1) once,
> and there's no need to re-read that byte to test BIT(0).
>
> Minor point ... I hate needless I/O. This isn't a critical
> path though.
>
Indeed. Exactly why I didn't try to optimize on I/O here :)
Cheers,
Peter.
--
goa is a state of mind
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