linux-kernel - [PATCH 6/15 -tip] x86: Add cpufeature for Scaleable bus speed

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Date:	Mon, 11 May 2009 22:19:27 +0530
From:	Jaswinder Singh Rajput <jaswinder@...nel.org>
To:	Ingo Molnar <mingo@...e.hu>
Cc:	"H. Peter Anvin" <hpa@...nel.org>,
	Robert Richter <robert.richter@....com>,
	x86 maintainers <x86@...nel.org>,
	LKML <linux-kernel@...r.kernel.org>
Subject: [PATCH 6/15 -tip] x86: Add cpufeature for Scaleable bus speed


X86_FEATURE_FSB_FREQ : Scaleable bus speed MSR_FSB_FREQ

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@...il.com>
---
 arch/x86/include/asm/cpufeature.h |    1 +
 arch/x86/kernel/cpu/intel.c       |    8 ++++++++
 2 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 97e54ad..8f789b5 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -160,6 +160,7 @@
 #define X86_FEATURE_CACHE_CTL	(7*32+ 5) /* Cache control MSRs		*/
 #define X86_FEATURE_HARD_POWERON (7*32+ 6) /* Hard Poweron configuration*/
 #define X86_FEATURE_SOFT_POWERON (7*32+ 7) /* Soft Poweron configuration*/
+#define X86_FEATURE_FSB_FREQ 	(7*32+ 8) /* Scaleable bus speed	*/
 
 /* Virtualization flags: Linux defined */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 239048d..aca1c7d 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -410,6 +410,12 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 			break;
 
 		case 9:	case 0xD:			/* Pentium M	*/
+			/* Hard Poweron configuration MSR_EBL_CR_POWERON*/
+			set_cpu_cap(c, X86_FEATURE_HARD_POWERON);
+			/* BBL_CR_CTL* MSRs (Cache control MSRs)	*/
+			set_cpu_cap(c, X86_FEATURE_CACHE_CTL);
+			break;
+
 		case 0xE:				/* Core		*/
 		case 0xF: case 0x17:			/* Core 2	*/
 		case 0x1C:				/* ATOM		*/
@@ -417,6 +423,8 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 			set_cpu_cap(c, X86_FEATURE_HARD_POWERON);
 			/* BBL_CR_CTL* MSRs (Cache control MSRs)	*/
 			set_cpu_cap(c, X86_FEATURE_CACHE_CTL);
+			/* Scaleable bus speed MSR_FSB_FREQ		*/
+			set_cpu_cap(c, X86_FEATURE_FSB_FREQ);
 			break;
 
 		case 0x16:				/* Celeron Core	*/
-- 
1.6.0.6



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