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Message-ID: <4A0A4829.8080709@jp.fujitsu.com>
Date: Wed, 13 May 2009 13:10:17 +0900
From: Hidetoshi Seto <seto.hidetoshi@...fujitsu.com>
To: Matthew Wilcox <matthew@....cx>,
"David S. Miller" <davem@...emloft.net>
CC: Jesse Barnes <jbarnes@...tuousgeek.org>, linux-pci@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH] PCI MSI: Yet another fix for MSI-X with NIU cards
Hi David,
Could you review & test following patch for your issue?
Thanks,
H.Seto
The NIU device refuses to allow accesses to MSI-X registers before MSI-X
is enabled. This patch fixes the problem by removing the read & write of
the mask register in msix_capability_init(). It will be safe since PCI
spac says the maskbit's state after reset is always 1 (= masked).
Reported-by: David S. Miller <davem@...emloft.net>
Signed-off-by: Hidetoshi Seto <seto.hidetoshi@...fujitsu.com>
---
drivers/pci/msi.c | 4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index 6f2e629..b680a5b 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -455,9 +455,7 @@ static int msix_capability_init(struct pci_dev *dev,
entry->msi_attrib.default_irq = dev->irq;
entry->msi_attrib.pos = pos;
entry->mask_base = base;
- entry->masked = readl(base + j * PCI_MSIX_ENTRY_SIZE +
- PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET);
- msix_mask_irq(entry, 1);
+ entry->masked = 1;
list_add_tail(&entry->list, &dev->msi_list);
}
--
1.6.3
--
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