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Message-Id: <1242190162.18059.82.camel@concordia>
Date: Wed, 13 May 2009 14:49:22 +1000
From: Michael Ellerman <michael@...erman.id.au>
To: Hidetoshi Seto <seto.hidetoshi@...fujitsu.com>
Cc: Matthew Wilcox <matthew@....cx>,
Jesse Barnes <jbarnes@...tuousgeek.org>,
"David S. Miller" <davem@...emloft.net>, linux-pci@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] Fix MSI-X with NIU cards
On Wed, 2009-05-13 at 13:40 +0900, Hidetoshi Seto wrote:
> Hidetoshi Seto wrote:
> > It seems that this issue was introduced by Matthew's commit:
> > commit f2440d9acbe866b917b16cc0f927366341ce9215
> > <quote>
> > @@ -435,11 +432,12 @@ static int msix_capability_init(struct pci_dev *dev,
> > entry->msi_attrib.is_msix = 1;
> > entry->msi_attrib.is_64 = 1;
> > entry->msi_attrib.entry_nr = j;
> > - entry->msi_attrib.maskbit = 1;
> > - entry->msi_attrib.masked = 1;
> > entry->msi_attrib.default_irq = dev->irq;
> > entry->msi_attrib.pos = pos;
> > entry->mask_base = base;
> > + entry->masked = readl(base + j * PCI_MSIX_ENTRY_SIZE +
> > + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET);
> > + msix_mask_irq(entry, 1);
> >
> > list_add_tail(&entry->list, &dev->msi_list);
> > }
> > </quote>
> >
> > I'm not sure why Matthew changed it to read/write...
>
> Sorry, I got it.
>
> The problem is not the bit[0] for mask, but the reserved bits[31::01].
> According to the Spec:
> "31::01 Reserved
> After reset, the state of these bits must be 0.
> However, for potential future use, software must preserve the value of
> these reserved bits when modifying the value of other Vector Control bits.
> If software modifies the value of these reserved bits, the result is
> undefined."
Yes that's what I was referring to about it being out of spec.
So to work around the NIU bug and be in spec I think we need to enable
MSI, then read the mask bits, then write them back with the mask bit
set.
cheers
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