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Message-ID: <20090522204300.GA10166@const.famille.thibault.fr>
Date: Fri, 22 May 2009 22:43:00 +0200
From: Samuel Thibault <samuel.thibault@...-lyon.org>
To: "Michael S. Zick" <lkml@...ethan.org>
Cc: Andi Kleen <andi@...stfloor.org>, linux-kernel@...r.kernel.org
Subject: Re: [BUG FIX] Make x86_32 uni-processor Atomic ops, Atomic
Michael S. Zick, le Fri 22 May 2009 15:32:41 -0500, a écrit :
> On Fri May 22 2009, Samuel Thibault wrote:
> > Michael S. Zick, le Fri 22 May 2009 14:53:39 -0500, a écrit :
> > > Ref: http://developer.intel.com/Assets/PDF/manual/253666.pdf
> > > Manual page: 3-590 PDF page: 638
> > > Summary: Processors prior to P-4 can take an interrupt between
> > > the read cycle and the write cycle. Which is why opcode 0xF0 exists.
> >
> > Where do you see page 638/639 talking about interrupts? It talks about
> > multi-processor machines.
>
> No - it talks about "exclusive memory access"
Right, that's still not interrupts.
> - You got bus master DMA in your test machine?
That's not related to the LOCK_PREFIX concern, which is about the
processor only, not interaction with other devices.
> Look people, I just reported what I found from testing -
What did you test, precisely?
Samuel
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