linux-kernel - Re: [VIA Support] was: [BUG FIX] Make x86

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Message-ID: <20090527124736.GU4024@prithivi.gnumonks.org>
Date:	Wed, 27 May 2009 14:47:36 +0200
From:	Harald Welte <HaraldWelte@...tech.com>
To:	"Michael S. Zick" <lkml@...ethan.org>
Cc:	"H. Peter Anvin" <hpa@...or.com>, Ingo Molnar <mingo@...e.hu>,
	Thomas Gleixner <tglx@...utronix.de>,
	linux-kernel@...r.kernel.org, Alan Cox <alan@...rguk.ukuu.org.uk>
Subject: Re: [VIA Support] was: [BUG FIX] Make x86_32 uni-processor Atomic
	ops, Atomic

On Wed, May 27, 2009 at 07:18:08AM -0500, Michael S. Zick wrote:
> On Sun May 24 2009, Harald Welte wrote:
> > 
> > Once I understand it in full detail, I can talk to the right people inside
> > CentaurLabs (VIA's CPU division).  
> > 
> > If somebody (optionally) can phrase a precise technical question that I can
> > directly forward to somebody with low-level x86 knowledge but no Linux background,
> > it would definitely help speeding up the process.
> > 
> 
> What is the PCI Cache Line size in the CX700?  In the CN896?

The chipset documentation doesn't say anything about that, I'd have to inquire
inside VIA.  I doubt any difference between CX700/CN896.

Also, setting the PCI config space register to a too small cache line size
(such as 32) on a system that supports more (say 64) doesn't really cause any
problems, but just reduces performance - as far as I know.

Setting it too big will cause trouble.  But since 32 is the default and
only on AMD and Intel CPU's it is increased, I see no issue here either.

-- 
- Harald Welte <HaraldWelte@...tech.com>	    http://linux.via.com.tw/
============================================================================
VIA Free and Open Source Software Liaison
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