linux-kernel - Re: VIA CPU PCI cache line size (Re: Linux 2.6.30-rc8 [also: VIA Support])

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Message-Id: <200906050843.42593.lkml@morethan.org>
Date:	Fri, 5 Jun 2009 08:43:40 -0500
From:	"Michael S. Zick" <lkml@...ethan.org>
To:	Harald Welte <HaraldWelte@...tech.com>
Cc:	Dave Jones <davej@...hat.com>,
	Linus Torvalds <torvalds@...ux-foundation.org>,
	Duane Griffin <duaneg@...da.com>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: VIA CPU PCI cache line size (Re: Linux 2.6.30-rc8 [also: VIA Support])

On Fri June 5 2009, Harald Welte wrote:
> On Thu, Jun 04, 2009 at 08:15:10PM -0400, Dave Jones wrote:
> 
> > I meant just doing something like this..
> > 
> > (untested)
> > 
> > I'm not sure if the clflush_size==0 case can happen, which is why
> > I left the fallback.  Maybe on ancient cpus?
> 
> this patch looks fine with me.  I didn't do any testing yet either, though.
> 

Although not coded as Dave J. suggests - I have been re-setting the
that value to the cpu cache line size for a week or two now.

It doesn't break anything in an obvious way - does seem to help.

Mike
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