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Message-ID: <4A2E82BA.7040905@zytor.com>
Date: Tue, 09 Jun 2009 08:41:46 -0700
From: "H. Peter Anvin" <hpa@...or.com>
To: Roland McGrath <roland@...hat.com>
CC: Petr Tesarik <ptesarik@...e.cz>, Sam Ravnborg <sam@...nborg.org>,
LKML <linux-kernel@...r.kernel.org>,
Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>,
Andi Kleen <andi@...stfloor.org>
Subject: Re: [PATCH] x86: clean up vdso-layout.lds.S
Roland McGrath wrote:
>
> You mean this one:
>
> /*
> * Align the actual code well away from the non-instruction data.
> * This is the best thing for the I-cache.
> */
> . = ALIGN(0x100);
>
> Reading the comment might make it obvious that it's intended for optimal
> code alignment. I suspect someone at the time told me 256 is as big as an
> I-cache line was ever likely to get. You could use L1_CACHE_BYTES instead
> I suppose.
>
Most likely 256 was chosen as a compromise between the the
then-documented value for coherency avoidance (128), future-proofing,
and waste.
I don't think we want to use different values on different platforms,
and end up with dramatically different vdsos when they still need to fit
in the same size envelope.
-hpa
--
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel. I don't speak on their behalf.
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