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Message-ID: <20090611023807.GA12407@Krystal>
Date: Wed, 10 Jun 2009 22:38:07 -0400
From: Mathieu Desnoyers <compudj@...stal.dyndns.org>
To: Huang Ying <ying.huang@...el.com>
Cc: Steven Rostedt <rostedt@...dmis.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Ingo Molnar <mingo@...e.hu>,
Andrew Morton <akpm@...ux-foundation.org>,
Thomas Gleixner <tglx@...utronix.de>,
Peter Zijlstra <peterz@...radead.org>,
Frederic Weisbecker <fweisbec@...il.com>,
Theodore Tso <tytso@....edu>,
Arnaldo Carvalho de Melo <acme@...hat.com>,
Lai Jiangshan <laijs@...fujitsu.com>,
"Martin J. Bligh" <mbligh@...igh.org>,
Christoph Hellwig <hch@...radead.org>,
Li Zefan <lizf@...fujitsu.com>,
"H. Peter Anvin" <hpa@...or.com>,
Hidetoshi Seto <seto.hidetoshi@...fujitsu.com>,
Masami Hiramatsu <mhiramat@...hat.com>
Subject: Re: [PATCH 3/3] ring-buffer: add design document
* Huang Ying (ying.huang@...el.com) wrote:
> On Thu, 2009-06-11 at 09:58 +0800, Steven Rostedt wrote:
> > On Thu, 11 Jun 2009, Huang Ying wrote:
> >
> > > On Thu, 2009-06-11 at 03:53 +0800, Steven Rostedt wrote:
> > > > +
> > > > +cmpxchg - hardware assisted atomic transaction that performs the following:
> > > > +
> > > > + A = B iff previous A == C
> > > > +
> > > > + R = cmpxchg(A, C, B) is saying that we replace A with B if and only if
> > > > + current A is equal to C, and we put the old (current) A into R
> > > > +
> > > > + R gets the previous A regardless if A is updated with B or not.
> > > > +
> > > > + To see if the update was successful a compare of R == C may be used.
> > >
> > > As far as I know, some architectures have no hardware assisted (NMI
> > > safe) cmpxchg. Is it OK to use cmpxchg in architecture-independent code?
> >
> > I can fall back to the lock solution for those archs without cmpxchg. It
> > is NMI safe, because we do spin_trylock() in NMI context. If we fail to
> > acquire the lock in NMI context, we simply drop the packet.
>
> Yes. For users do not care about packet drop, it is acceptable. But
> please select the implementation at run-time instead of build time.
> Because on some architecture such as ARM, whether CPU has cmpxchg
> support is determined at run-time.
>
> > Are these archs without cmpxchg and NMIs, a concern for you?
>
> ARM has no cmpxchg until ARM v6, but it has NMI like mechanism named
> FIQ.
>
One could probably adapt the cmpxchg for earlier ARM so it disables
FIQs. Note that the current limitation is that there is only a
fiq disable, not a fiq save/restore.
Mathieu
> Best Regards,
> Huang Ying
>
>
--
Mathieu Desnoyers
OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F BA06 3F25 A8FE 3BAE 9A68
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