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Message-ID: <20090611112649.719a0eb5@jbarnes-g45>
Date: Thu, 11 Jun 2009 11:26:49 -0700
From: Jesse Barnes <jesse.barnes@...el.com>
To: "Rafael J. Wysocki" <rjw@...k.pl>
Cc: pm list <linux-pm@...ts.linux-foundation.org>,
Linux PCI <linux-pci@...r.kernel.org>,
LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/2] PCI PM: Follow PCI_PM_CTRL_NO_SOFT_RESET during
transitions from D3
On Mon, 18 May 2009 22:51:12 +0200
"Rafael J. Wysocki" <rjw@...k.pl> wrote:
> From: Rafael J. Wysocki <rjw@...k.pl>
>
> According to the PCI PM specification (PCI Bus Power Management
> Interface Specification, Rev. 1.2, Section 5.4.1) we are supposed to
> reinitialize devices that have PCI_PM_CTRL_NO_SOFT_RESET clear during
> all transitions from PCI_D3hot to PCI_D0, but we only do it if the
> device's current_state field is equal to PCI_UNKNOWN.
>
> This may lead to problems if a device with PCI_PM_CTRL_NO_SOFT_RESET
> unset is put into PCI_D3hot at run time by its driver and
> pci_set_power_state() is used to put it back into PCI_D0, because in
> that case the device will remain uninitialized after
> pci_set_power_state() has returned. Prevent that from happening by
> modifying pci_raw_set_power_state() to reinitialize devices with
> PCI_PM_CTRL_NO_SOFT_RESET unset during all transitions from D3 to D0.
>
> Signed-off-by: Rafael J. Wysocki <rjw@...k.pl>
> ---
> drivers/pci/pci.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> Index: linux-2.6/drivers/pci/pci.c
> ===================================================================
> --- linux-2.6.orig/drivers/pci/pci.c
> +++ linux-2.6/drivers/pci/pci.c
> @@ -480,6 +480,8 @@ static int pci_raw_set_power_state(struc
> pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
> pmcsr |= state;
> break;
> + case PCI_D3hot:
> + case PCI_D3cold:
> case PCI_UNKNOWN: /* Boot-up */
> if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
> && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
>
Applied to my linux-next branch, thanks Rafael. I've also included
stable@...nel.org in the cc, since this is a small but important fix.
--
Jesse Barnes, Intel Open Source Technology Center
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