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Message-Id: <200906150810.15799.lkml@morethan.org>
Date: Mon, 15 Jun 2009 08:10:13 -0500
From: "Michael S. Zick" <lkml@...ethan.org>
To: Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Cc: Harald Welte <HaraldWelte@...tech.com>,
Dave Jones <davej@...hat.com>,
Linus Torvalds <torvalds@...ux-foundation.org>
Subject: TSC features, was: Re: [PATCH 1/2] CPUFREQ: Enable acpi-cpufreq driver for VIA/Centaur CPUs
On Mon June 8 2009, Linus Torvalds wrote:
>
> On Mon, 8 Jun 2009, Harald Welte wrote:
> >
> > The VIA/Centaur C7, C7-M and Nano CPU's all support ACPI based cpu p-states
> > using a MSR interface. The Linux driver just never made use of it, since in
> > addition to the check for the EST flag it also checked if the vendor is Intel.
> >
> > Signed-off-by: Harald Welte <HaraldWelte@...tech.com>
> > ---
> > arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c | 3 ++-
> > 1 files changed, 2 insertions(+), 1 deletions(-)
> >
> > diff --git a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
> > index 208ecf6..ee03585 100644
> > --- a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
> > +++ b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
> > @@ -90,7 +90,8 @@ static int check_est_cpu(unsigned int cpuid)
> > {
> > struct cpuinfo_x86 *cpu = &cpu_data(cpuid);
> >
> > - if (cpu->x86_vendor != X86_VENDOR_INTEL ||
> > + if ((cpu->x86_vendor != X86_VENDOR_INTEL &&
> > + cpu->x86_vendor != X86_VENDOR_CENTAUR) ||
> > !cpu_has(cpu, X86_FEATURE_EST))
>
> Hmm. This all really should be just
>
> static int check_est_cpu(unsigned int cpuid)
> {
> struct cpuinfo_x86 *cpu = &cpu_data(cpuid);
> return cpu_has(cpu, X86_FEATURE_EST);
> }
>
> I suspect, with no vendor tests. That's the whole _point_ of CPU features,
> after all.
>
Following that same logic, shouldn't this chunk be based on CPU features also?
(Spotted while tracking down why the non-stop TSC wasn't being used on VIA):
#if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86)
static void tsc_check_state(int state)
{
switch (boot_cpu_data.x86_vendor) {
case X86_VENDOR_AMD:
case X86_VENDOR_INTEL:
/*
* AMD Fam10h TSC will tick in all
* C/P/S0/S1 states when this bit is set.
*/
if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
return;
/*FALL THROUGH*/
default:
/* TSC could halt in idle, so notify users */
if (state > ACPI_STATE_C1)
mark_tsc_unstable("TSC halts in idle");
}
}
#else
static void tsc_check_state(int state) { return; }
#endif
Mike
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