linux-kernel - Re: [tip:perfcounters/core] perf_counter: x86: Fix call-chain support to use NMI-safe methods

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Message-ID: <20090615183840.GA6520@Krystal>
Date:	Mon, 15 Jun 2009 14:38:40 -0400
From:	Mathieu Desnoyers <mathieu.desnoyers@...ymtl.ca>
To:	Ingo Molnar <mingo@...e.hu>
Cc:	Linus Torvalds <torvalds@...ux-foundation.org>, mingo@...hat.com,
	hpa@...or.com, paulus@...ba.org, acme@...hat.com,
	linux-kernel@...r.kernel.org, a.p.zijlstra@...llo.nl,
	penberg@...helsinki.fi, vegard.nossum@...il.com, efault@....de,
	jeremy@...p.org, npiggin@...e.de, tglx@...utronix.de,
	linux-tip-commits@...r.kernel.org
Subject: Re: [tip:perfcounters/core] perf_counter: x86: Fix call-chain
	support to use NMI-safe methods

* Ingo Molnar (mingo@...e.hu) wrote:
> 
> * Mathieu Desnoyers <mathieu.desnoyers@...ymtl.ca> wrote:
> 
> > Hrm, would it be possible to save the c2 register upon nmi handler 
> > entry and restore it before iret instead ? This would ensure a 
> > nmi-interrupted page fault handler would continue what it was 
> > doing with a non-corrupted cr2 register after returning from nmi.
> > 
> > Plus, this involves no modification to the page fault handler fast 
> > path.
> 
> I guess this kind of nesting would work too - assuming the cr2 can 
> be written to robustly.
> 
> And i suspect CPU makers pull off a few tricks to stage the cr2 info 
> away from the page fault entry execution asynchronously, so i'd not 
> be surprised if writing to it uncovered unknown-so-far side-effects 
> in CPU implementations.
> 
> If possible i wouldnt want to rely on such a narrowly possible hack 
> really - any small change in CPU specs could cause problems years 
> down the line.
> 
> The GUP based method is pretty generic though - and can be used on 
> other architectures as well. It's not as fast as direct access 
> though.
> 
> 	Ingo

I guess. However, having the ability to call module code in NMI handler
context without having to fear for page fault handler re-entrancy (on
x86 32) seems like an interesting overall simplification of nmi-handler
rules. It is currently far from trivial to write code aimed at NMI
handler context. I mean.. LTTng should not have to run
vmalloc_sync_all() after loading its modules as it currently does.

Maybe it would be worth trying the save/restore cr2 approach and test to
figure out how a large variety of machines react. The fact is that
hypervisor code already writes into the cr2 register :

kvm/vmx.c :
vmx_vcpu_run()
...
                "mov %%"R"ax, %%cr2 \n\t"

Mathieu



-- 
Mathieu Desnoyers
OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F  BA06 3F25 A8FE 3BAE 9A68
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