linux-kernel - Double-switching SMP alternatives

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Message-ID: <alpine.LSU.2.00.0906202205150.29073@fbirervta.pbzchgretzou.qr>
Date:	Sat, 20 Jun 2009 22:06:13 +0200 (CEST)
From:	Jan Engelhardt <jengelh@...ozas.de>
To:	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Double-switching SMP alternatives

Hi,

in dmesg of a 2.6.25, I am finding:

Checking 'hlt' instruction... OK.
SMP alternatives: switching to UP code
[...]
SMP alternatives: switching to SMP code
Booting processor 1/1 ip 4000
Initializing CPU#1
Calibrating delay using timer specific routine.. 5581.16 BogoMIPS 
(lpj=2790583)
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 512K
CPU: Physical Processor ID: 0
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#1.
CPU1: Intel P4/Xeon Extended MCE MSRs (12) available
CPU1: Thermal monitoring enabled
CPU1: Intel(R) Xeon(TM) CPU 2.80GHz stepping 07
Booting processor 2/6 ip 4000
Initializing CPU#2
[...]

Would not it make sense to skip the first switch to UP?

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