linux-kernel - Re: perf_counter Atom patch

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Message-ID: <7c86c4470906230127g4f574b61p24f109c7a94c6e39@mail.gmail.com>
Date:	Tue, 23 Jun 2009 10:27:47 +0200
From:	stephane eranian <eranian@...glemail.com>
To:	Yong Wang <yong.y.wang@...ux.intel.com>
Cc:	"Wang, Yong Y" <yong.y.wang@...el.com>,
	Ingo Molnar <mingo@...e.hu>,
	Peter Zijlstra <a.p.zijlstra@...llo.nl>,
	LKML <linux-kernel@...r.kernel.org>,
	Paul Mackerras <paulus@...ba.org>,
	Andi Kleen <andi@...stfloor.org>
Subject: Re: perf_counter Atom patch

Hi,

On Tue, Jun 23, 2009 at 9:59 AM, Yong Wang<yong.y.wang@...ux.intel.com> wrote:
> On Tue, Jun 23, 2009 at 09:45:03AM +0200, stephane eranian wrote:
>>
>> Unfortunately, I don't have a N270 to compare with your results.
>> We need to verify whether or not N270 implements the fixed counters.
>> Does it report architected perfmon v3 or v1?
>>
>
> All Atom processors report perfmon v3 as specified in SDM. N270 is no
> exception.
>
V3 does not set a minimal number of fixed counters, could be zero. But
that seems
odd. Let me ask around.

>> > The return value of CPUID(0xa) is indeed bogus, too and there is another quirk for that in
>> > intel_pmu_init() in arch/x86/kernel/cpu/perf_counter.c
>> >
>> > x86_pmu.num_counters_fixed ?? ?? ??= max((int)edx.split.num_counters_fixed, 3);
>> >
>> > Is this what you were talking about?
>>
>> Not quite, because with the max() you'd have a problem on Intel Core
>> Duo/Solo processors
>> as they do implement the first generation of architected perfmon and
>> that one did not have
>> fixed counters. So you'd have to special case family=6 model=14.
>
> That has been taken into account actually. Only perfmon v2 and above are
> supported as you see in intel_pmu_init().
>
>        if (version < 2)
>                return -ENODEV;
>
I assume this is a current limitation of the implementation. If you
see version <  2
you could simply consider having 0 fixed counters and everything else would work
as expected. But there is a catch, unfortunately, in that there is erratum AE49
which says that there is only one enable bit to control the two generic counters
on Core Duo/Solo.
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