linux-kernel - Re: perf_counter Atom patch

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Message-Id: <1245748205.19816.1550.camel@twins>
Date:	Tue, 23 Jun 2009 11:10:05 +0200
From:	Peter Zijlstra <a.p.zijlstra@...llo.nl>
To:	Yong Wang <yong.y.wang@...ux.intel.com>
Cc:	eranian@...il.com, "Wang, Yong Y" <yong.y.wang@...el.com>,
	Ingo Molnar <mingo@...e.hu>,
	LKML <linux-kernel@...r.kernel.org>,
	Paul Mackerras <paulus@...ba.org>,
	Andi Kleen <andi@...stfloor.org>
Subject: Re: perf_counter Atom patch

On Tue, 2009-06-23 at 16:34 +0800, Yong Wang wrote:
> > you could simply consider having 0 fixed counters and everything else would work
> > as expected. But there is a catch, unfortunately, in that there is erratum AE49
> > which says that there is only one enable bit to control the two generic counters
> > on Core Duo/Solo.

Ah, that's similar to P6 like machines. The P6 docs say that to disable
a counter you should simply write all zeros (except the EN bit for ctr0)
to the control register (IIRC).

I suppose we could do something similar on these errata cores, make
x86_pmu_disable_counter() write ARCH_PERFMON_EVENTSEL0_ENABLE instead.

Would that work?

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