linux-kernel - Re: [PATCH 1/2] FRV: Implement atomic64

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Message-ID: <4A4DFC17.4090809@cosmosbay.com>
Date:	Fri, 03 Jul 2009 14:39:51 +0200
From:	Eric Dumazet <dada1@...mosbay.com>
To:	Ingo Molnar <mingo@...e.hu>
CC:	Eric Dumazet <eric.dumazet@...il.com>,
	Linus Torvalds <torvalds@...ux-foundation.org>,
	David Howells <dhowells@...hat.com>, akpm@...ux-foundation.org,
	paulus@...ba.org, arnd@...db.de, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/2] FRV: Implement atomic64_t

Ingo Molnar a écrit :
> * Eric Dumazet <eric.dumazet@...il.com> wrote:
> 
>> My last suggestion would be :
>>
>> static inline unsigned long long atomic64_read(const atomic64_t *ptr)
>> {
>> 	unsigned long long res;
>>
>> 	asm volatile(
>> 		"mov     %%ebx, %%eax\n\t"
>> 		"mov     %%ecx, %%edx\n\t"
>> 		LOCK_PREFIX "cmpxchg8b %1\n"
>> 			: "=A" (res)
>> 			: "m" (*ptr)
>> 		);
>> 	return res;
>> }
>>
>> ebx/ecx being read only, and their value can be random, they are 
>> not even mentioned in asm constraints, so gcc is allowed to keep 
>> useful values in these registers.
>>
>> So the following (stupid) example
>>
>>         for (i = 0; i < 10000000; i++) {
>>                 res += atomic64_read(&myvar);
>>         }
>>
>> gives :
>>         xorl    %esi, %esi
>> .L2:
>>         mov     %ebx, %eax
>>         mov     %ecx, %edx
>>         lock;cmpxchg8b myvar
>>         addl    %eax, %ecx
>>         adcl    %edx, %ebx
>>         addl    $1, %esi
>>         cmpl    $10000000, %esi
>>         jne     .L2
> 
> Ok, agreed. We dont want to inline it - cmpxchg8b is way too fat - 
> but your code above is a valid optimization for the out-of-line 
> variant as well. So i have applied it as such, will post the whole 
> atomic64_t series soon, after some testing.

I just changed "=A" constraint to "+A" or gcc could use %edx/%eax in "ptr"
address computation. I discovered this after crashing my box :)


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