linux-kernel - Re: [tip:perfcounters/urgent] x86: atomic64: The atomic64_t data type should be 8 bytes aligned on 32-bit too

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Message-ID: <4A4E4493.3040009@zytor.com>
Date:	Fri, 03 Jul 2009 10:49:07 -0700
From:	"H. Peter Anvin" <hpa@...or.com>
To:	Linus Torvalds <torvalds@...ux-foundation.org>
CC:	mingo@...hat.com, paulus@...ba.org, acme@...hat.com,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	eric.dumazet@...il.com, a.p.zijlstra@...llo.nl, efault@....de,
	arnd@...db.de, fweisbec@...il.com, dhowells@...hat.com,
	Andrew Morton <akpm@...ux-foundation.org>, tglx@...utronix.de,
	Ingo Molnar <mingo@...e.hu>
Subject: Re: [tip:perfcounters/urgent] x86: atomic64: The atomic64_t data
 type should be 8 bytes aligned on 32-bit too

Linus Torvalds wrote:
> 
> It's not necessarily even about "two cachelines". It's true that crossing 
> cachelines is extra painful, but from a CPU core angle, there's another 
> access width that matters almost as much, namely the width of the bus 
> between the core and the L1 cache. If it's not aligned to that, the core 
> needs to do each 8-byte read/write as two accesses, even if it's to the 
> same cacheline, and that complicates things.
> 
> The cacheline itself is generally larger than the cache access width. I 
> could easily see a 64B cacheline, but a 256b (32B) bus between the cache 
> and the core.
> 
> Making the atomics be naturally aligned means that you never cross either 
> one, of course.
> 

Sometimes, of course, that down-mux is where alignment happens, too.
Either which way, I don't think there is any doubt that unaligned
atomics are just asking for trouble.

	-hpa

-- 
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel.  I don't speak on their behalf.

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