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Message-Id: <1247789146-18786-20-git-send-email-vapier@gentoo.org>
Date: Thu, 16 Jul 2009 20:05:44 -0400
From: Mike Frysinger <vapier@...too.org>
To: linux-kernel@...r.kernel.org
Cc: uclinux-dist-devel@...ckfin.uclinux.org,
Graf Yang <graf.yang@...log.com>
Subject: [PATCH 19/21] Blackfin: add CPLB entries for Core B on-chip L1 SRAM regions
From: Graf Yang <graf.yang@...log.com>
The Blackfin SMP port was missing CPLB entries for Core B on-chip L1 SRAM
regions. Any code that attempted to use these would wrongly crash due to
a CPLB miss.
Signed-off-by: Graf Yang <graf.yang@...log.com>
Signed-off-by: Mike Frysinger <vapier@...too.org>
---
arch/blackfin/kernel/cplb-nompu/cplbinit.c | 23 +++++++++++++++++------
1 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index d6c0677..685f160 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -72,13 +72,24 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
}
/* Cover L1 memory. One 4M area for code and data each is enough. */
- if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
- d_tbl[i_d].addr = L1_DATA_A_START;
- d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
+ if (cpu == 0) {
+ if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
+ d_tbl[i_d].addr = L1_DATA_A_START;
+ d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
+ }
+ i_tbl[i_i].addr = L1_CODE_START;
+ i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
}
- i_tbl[i_i].addr = L1_CODE_START;
- i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
-
+#ifdef CONFIG_SMP
+ else {
+ if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
+ d_tbl[i_d].addr = COREB_L1_DATA_A_START;
+ d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
+ }
+ i_tbl[i_i].addr = COREB_L1_CODE_START;
+ i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
+ }
+#endif
first_switched_dcplb = i_d;
first_switched_icplb = i_i;
--
1.6.3.3
--
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