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Message-ID: <20090901132824.GN19719@n2100.arm.linux.org.uk>
Date: Tue, 1 Sep 2009 14:28:24 +0100
From: Russell King - ARM Linux <linux@....linux.org.uk>
To: Steven Walter <stevenrwalter@...il.com>
Cc: David Xiao <dxiao@...adcom.com>,
Laurent Pinchart <laurent.pinchart@...asonboard.com>,
Ben Dooks <ben-linux@...ff.org>,
Hugh Dickins <hugh.dickins@...cali.co.uk>,
Robin Holt <holt@....com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
v4l2_linux <linux-media@...r.kernel.org>,
"linux-arm-kernel@...ts.arm.linux.org.uk"
<linux-arm-kernel@...ts.arm.linux.org.uk>
Subject: Re: How to efficiently handle DMA and cache on ARMv7 ? (was "Is
get_user_pages() enough to prevent pages from being swapped out ?")
On Tue, Aug 25, 2009 at 08:53:29AM -0400, Steven Walter wrote:
> On Thu, Aug 6, 2009 at 6:25 PM, Russell King - ARM
> Linux<linux@....linux.org.uk> wrote:
> [...]
> > As far as userspace DMA coherency, the only way you could do it with
> > current kernel APIs is by using get_user_pages(), creating a scatterlist
> > from those, and then passing it to dma_map_sg(). While the device has
> > ownership of the SG, userspace must _not_ touch the buffer until after
> > DMA has completed.
> [...]
>
> Would that work on a processor with VIVT caches? It seems not. In
> particular, dma_map_page uses page_address to get a virtual address to
> pass to map_single(). map_single() in turn uses this address to
> perform cache maintenance. Since page_address() returns the kernel
> virtual address, I don't see how any cache-lines for the userspace
> virtual address would get invalidated (for the DMA_FROM_DEVICE case).
You are correct.
> If that's true, then what is the correct way to allow DMA to/from a
> userspace buffer with a VIVT cache? If not true, what am I missing?
I don't think you read what I said (but I've also forgotten what I did
say).
To put it simply, the kernel does not support DMA direct from userspace
pages. Solutions which have been proposed in the past only work with a
sub-set of conditions (such as the one above only works with VIPT
caches.)
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