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Message-Id: <1253133870-25140-5-git-send-email-tabbott@ksplice.com>
Date: Wed, 16 Sep 2009 16:44:29 -0400
From: Tim Abbott <tabbott@...lice.com>
To: x86@...nel.org
Cc: Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>,
"H. Peter Anvin" <hpa@...or.com>, linux-kernel@...r.kernel.org,
Sam Ravnborg <sam@...nborg.org>,
Tim Abbott <tabbott@...lice.com>
Subject: [PATCH v3 4/5] x86: Use section .data.page_aligned for the idt_table.
The .data.idt section is just squashed into the .data.page_aligned
output section by the linker script anyway, so it might as well be in
the .data.page_aligned section.
This eliminates all references to .data.idt on x86.
Signed-off-by: Tim Abbott <tabbott@...lice.com>
Cc: Ingo Molnar <mingo@...hat.com>
---
arch/x86/kernel/traps.c | 6 ++----
arch/x86/kernel/vmlinux.lds.S | 1 -
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index 8326492..ea23d3b 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -73,11 +73,9 @@ char ignore_fpu_irq;
/*
* The IDT has to be page-aligned to simplify the Pentium
- * F0 0F bug workaround.. We have a special link segment
- * for this.
+ * F0 0F bug workaround.
*/
-gate_desc idt_table[NR_VECTORS]
- __attribute__((__section__(".data.idt"))) = { { { { 0, 0 } } }, };
+gate_desc idt_table[NR_VECTORS] __page_aligned_data = { { { { 0, 0 } } }, };
#endif
DECLARE_BITMAP(used_vectors, NR_VECTORS);
diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S
index 5c7826d..7d6cef3 100644
--- a/arch/x86/kernel/vmlinux.lds.S
+++ b/arch/x86/kernel/vmlinux.lds.S
@@ -112,7 +112,6 @@ SECTIONS
#endif
PAGE_ALIGNED_DATA(PAGE_SIZE)
- *(.data.idt)
CACHELINE_ALIGNED_DATA(CONFIG_X86_L1_CACHE_BYTES)
--
1.6.3.3
--
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