linux-kernel - Re: [PATCH 1/3] pci: determine CLS more intelligently

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Message-ID: <20090917103131.55eca691@jbarnes-g45>
Date:	Thu, 17 Sep 2009 10:31:31 -0700
From:	Jesse Barnes <jbarnes@...tuousgeek.org>
To:	Tejun Heo <tj@...nel.org>
Cc:	Greg KH <greg@...ah.com>, Robert Hancock <hancockr@...w.ca>,
	Alan Cox <alan@...rguk.ukuu.org.uk>, linux-pci@...r.kernel.org,
	Linux Kernel <linux-kernel@...r.kernel.org>,
	Daniel Ritz <daniel.ritz@....ch>,
	Dominik Brodowski <linux@...inikbrodowski.net>,
	Kenji Kaneshige <kaneshige.kenji@...fujitsu.com>,
	Axel Birndt <towerlexa@....de>,
	Benjamin Herrenschmidt <benh@...nel.crashing.org>,
	Ingo Molnar <mingo@...e.hu>,
	Thomas Gleixner <tglx@...utronix.de>,
	Tony Luck <tony.luck@...el.com>,
	David Miller <davem@...emloft.net>
Subject: Re: [PATCH 1/3] pci: determine CLS more intelligently

On Sat, 04 Jul 2009 14:08:57 +0900
Tejun Heo <tj@...nel.org> wrote:

> Till now, CLS has been determined either by arch code or as
> L1_CACHE_BYTES.  Only x86 and ia64 set CLS explicitly and x86 doesn't
> always get it right.  On most configurations, the chance is that
> firmware configures the correct value during boot.
> 
> This patch makes pci_init() determine CLS by looking at what firmware
> has configured.  It scans all devices and if all non-zero values
> agree, the value is used.  If none is configured or there is a
> disagreement, pci_dfl_cache_line_size is used.  arch can set the dfl
> value (via PCI_CACHE_LINE_BYTES or pci_dfl_cache_line_size) or
> override the actual one.
> 
> ia64, x86 and sparc64 updated to set the default cls instead of the
> actual one.
> 
> While at it, declare pci_cache_line_size and pci_dfl_cache_line_size
> in pci.h and drop private declarations from arch code.

This sounds like a good improvement (though I share Ingo's concerns
about platform breakage here).  Can you respin the patchset against my
linux-next current tree?

Thanks,
-- 
Jesse Barnes, Intel Open Source Technology Center
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