linux-kernel - Re: [PATCH 0/2]: Get perf counters working on D-cache aliasing cpus.

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <1253277096.8439.127.camel@twins>
Date:	Fri, 18 Sep 2009 14:31:36 +0200
From:	Peter Zijlstra <a.p.zijlstra@...llo.nl>
To:	David Miller <davem@...emloft.net>
Cc:	linux-kernel@...r.kernel.org, mingo@...e.hu, jens.axboe@...cle.com
Subject: Re: [PATCH 0/2]: Get perf counters working on D-cache aliasing
 cpus.

On Tue, 2009-09-08 at 05:10 -0700, David Miller wrote:
> With Jen's Axboe's basic sparc counter patch in my tree I started
> playing with it on sparc64.  Turns out it won't work on anything
> pre-Niagara.
> 
> The issue is D-cache aliasing between the kernel side mapping
> and the user side mapping of the perf event ring buffer.
> 
> The following two patches attempt to address this issue and
> are working properly on my test machine.

Dave,

Ingo just reminded me that we might want to do splice support for perf
stuff. My plan was to have the splice thing allocate a new page, flip
with a filled one from the buffer and send the filled one down to the
splice consumer.

Now having vmap'ed all that complicates stuff enourmously.

Would it also work if we use order-1 pages on your platform instead of
order-0, so that they are properly aligned for the d-cache?

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/