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Message-Id: <de70b67245e012ab0c11b520a721989b@localhost>
Date: Fri, 18 Sep 2009 19:12:45 -0700
From: Kevin Cernekee <cernekee@...il.com>
To: Ralf Baechle <ralf@...ux-mips.org>
Cc: <linux-mips@...ux-mips.org>, <linux-kernel@...r.kernel.org>
Subject: [PATCH] MIPS: Avoid destructive invalidation on partial L2 cachelines
This extends commit a8ca8b64e3fdfec17679cba0ca5ce6e3ffed092d to cover
the board cache code.
Signed-off-by: Kevin Cernekee <cernekee@...il.com>
---
arch/mips/mm/sc-mips.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index b55c2d1..5ab5fa8 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -32,6 +32,11 @@ static void mips_sc_wback_inv(unsigned long addr, unsigned long size)
*/
static void mips_sc_inv(unsigned long addr, unsigned long size)
{
+ unsigned long lsize = cpu_scache_line_size();
+ unsigned long almask = ~(lsize - 1);
+
+ cache_op(Hit_Writeback_Inv_SD, addr & almask);
+ cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask);
blast_inv_scache_range(addr, addr + size);
}
--
1.6.3.1
--
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