linux-kernel - Re: [PATCH 0/4] jump label patches

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Date:	Mon,  5 Oct 2009 23:04:10 -0700 (PDT)
From:	Roland McGrath <roland@...hat.com>
To:	Jason Baron <jbaron@...hat.com>
Cc:	linux-kernel@...r.kernel.org, mingo@...e.hu,
	mathieu.desnoyers@...ymtl.ca, tglx@...utronix.de,
	rostedt@...dmis.org, ak@...e.de, rth@...hat.com,
	mhiramat@...hat.com
Subject: Re: [PATCH 0/4] jump label patches

I think text_poke_fixup() is a good safe place to start, and it seems wise
to merge a version using that before worrying anything subtler.  But it's
almost surely overkill and makes the enable/disable switching cost pretty
huge.  The rules as documented by Intel seem to indicate that simple
self-modification can work for UP and for SMP there should be some scheme
with IPIs that is not too terrible.  

Those can entail a multi-phase modification like the int3 patching style,
but int3 is not the only way to do it.  int3 has the benefit of being a
one-byte instruction you can patch in, but also the downside of requiring
the trap handling hair.  Another approach is:

start:
	   .balign 2
	2: nopl
	7: ...

phase 1:
	2: jmp 7
	4: <last 3 bytes of nopl>
	7: ...

phase 2:
	2: jmp 7
	4: {last 3 bytes of "jmp .Ldo_trace"}
	7: ...

phase 3:
	2: jmp .Ldo_trace
	7: ...

A scheme like that requires that the instruction to be patched be 2-byte
aligned so that the two-byte "jmp .+3" can be an atomic store not
straddling a word boundary.  On x86-64 (and, according to the Intel book,
everything >= Pentium), you can atomically store 8 bytes when aligned.  So
there you will usually actually be able to do this in one or two phases to
cover each particular 5 byte range with adequately aligned stores.

Thanks,
Roland
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