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Message-Id: <20091007.134626.238756485.davem@davemloft.net>
Date:	Wed, 07 Oct 2009 13:46:26 -0700 (PDT)
From:	David Miller <davem@...emloft.net>
To:	eranian@...il.com, eranian@...glemail.com
Cc:	paulus@...ba.org, a.p.zijlstra@...llo.nl,
	linux-kernel@...r.kernel.org, mingo@...e.hu,
	perfmon2-devel@...ts.sf.net
Subject: Re: [PATCH 2/2] perf_events: add event constraints support for
 Intel processors

From: stephane eranian <eranian@...glemail.com>
Date: Wed, 7 Oct 2009 14:31:58 +0200

> What PPC does is probably the only way to do this given the interface between
> generic and machine-specific code. The one advantage I see is that it works
> inside an event group but also across event groups because that code does not
> look at group boundary, it only looks at the events and the number of available
> registers. The downside is that you duplicate state.
> 
> Did I get this right, Paul?

That's basically how his code works, yes.  I intend on duplicating
it to some extent on sparc64 since I'm operating in a similar
problem space.

So if at least some of this engine went to a generic place, there'd
be at least a 3rd user :-)
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