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Message-ID: <b8bf37780910250937x14b8f008xd8443fe004749403@mail.gmail.com>
Date: Sun, 25 Oct 2009 14:37:57 -0200
From: André Goddard Rosa <andre.goddard@...il.com>
To: Henrique de Moraes Holschuh <hmh@....eng.br>
Cc: gregkh@...e.de, alan@...ux.intel.com,
Andrew Morton <akpm@...ux-foundation.org>, adobriyan@...il.com,
linux list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 2/2] serial: cascade needless conditionals
Hi, Henrique!
On 10/25/09, Henrique de Moraes Holschuh <hmh@....eng.br> wrote:
> On Sun, 25 Oct 2009, André Goddard Rosa wrote:
>> if (flags == UPF_SPD_HI)
>> altbaud = 57600;
>> - if (flags == UPF_SPD_VHI)
>> + else if (flags == UPF_SPD_VHI)
>> altbaud = 115200;
>> - if (flags == UPF_SPD_SHI)
>> + else if (flags == UPF_SPD_SHI)
>> altbaud = 230400;
>> - if (flags == UPF_SPD_WARP)
>> + else if (flags == UPF_SPD_WARP)
>> altbaud = 460800;
>
> This changes code behaviour if more than one bit is set (which might never
> happen for all I know...). You should invert the order of the tests if you
> want to make sure it is side-effect-free.
>
Do you mind explaining why? Notice that it's not (var & flag), it's =='.
Can flags be equal more than one flag at the same time?
Thanks,
André
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