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Date:	Mon, 26 Oct 2009 11:52:11 -0700
From:	Yinghai Lu <>
To:	Kenji Kaneshige <>
CC:	Jesse Barnes <>,
	"" <>,
	"" <>,
	Alex Chiang <>,
	Ivan Kokshaysky <>,
	Bjorn Helgaas <>
Subject: Re: [PATCH] pci: pciehp update the slot bridge res to get big range
 for pcie devices

Yinghai Lu wrote:
> Kenji Kaneshige wrote:
>> I understand you need to touch I/O base/limit and Mem base/limit. But
>> I don't understand why you also need to update bridge's BARs. Could
>> you please explain a little more about it?
>> Just in case, my terminology "bridge's BARs" is Base Address Register
>> 0 (offset 0x10) and Base Address Register 1 (offset 0x14) in the
>> (type 1) configuration space header of the bridge.
> i mean 0x1c, 0x20, 0x28
> did not notice that bridge device's 0x10, 0x14 are used...
> if port service need to use 0x10, 0x14, and the device is enabled, we should touch 0x10, and 0x14.

after check the code, if 

pci_bridge_assign_resources ==> pdev_assign_resources_sorted ==>  pdev_sort_resources

will not touch 0x10 and 0x14, if those resource is claimed by port service.

/* Sort resources by alignment */
void pdev_sort_resources(struct pci_dev *dev, struct resource_list *head)
        int i;
        for (i = 0; i < PCI_NUM_RESOURCES; i++) {
                struct resource *r;
                struct resource_list *list, *tmp;
                resource_size_t r_align;
                r = &dev->resource[i];
                if (r->flags & IORESOURCE_PCI_FIXED)
                if (!(r->flags) || r->parent)

r->parent != NULL, will make it skip those two.

So -v3 should be safe.


Yinghai Lu

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