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Date:	Mon, 26 Oct 2009 17:45:25 -0700 (PDT)
From:	David Miller <>
Subject: Re: [PATCH ide] : Increase WAIT_DRQ to support slow CF cards

From: Robert Hancock <>
Date: Mon, 26 Oct 2009 18:34:57 -0600

> This has come up before:
> I think this timeout should not even exist. libata has no such timeout
> (only the overall command completion timeout), and I can't find any
> reference in current ATA specs to the device being required to raise
> DRQ in any particular amount of time.

So is the issue that, whilst we should wait for BUSY to clear,
waiting around for DRQ is unreasonable?

It seems that WAIT_DRQ is passed to ide_wait_stat() but that
only controls how long we wait for BUSY to clear, the ATA_DRQ
'bad' bit we pass there only gets probed in a fixed limit loop:

	for (i = 0; i < 10; i++) {
		stat = tp_ops->read_status(hwif);

		if (OK_STAT(stat, good, bad)) {
			*rstat = stat;
			return 0;
	*rstat = stat;
	return -EFAULT;

Therefore, if increasing WAIT_DRQ helps things for people, it's
because the BUSY bit needs that much time to clear in these

The talking in that thread seems to state that the ATA layer
waits only for BUSY to clear, it does not wait for DRQ.  But
from the data we're seeing here, it is in fact BUSY which needs
so much more time to clear so removing the DRQ bit probe to
be more like ATA won't fix anything.
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