linux-kernel - Re: [PATCH] x86, mce: short output of MCE banks ownership information

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Message-ID: <4AE93B42.5040605@jp.fujitsu.com>
Date:	Thu, 29 Oct 2009 15:50:42 +0900
From:	Hidetoshi Seto <seto.hidetoshi@...fujitsu.com>
To:	Roland Dreier <rdreier@...co.com>
CC:	linux-kernel@...r.kernel.org, x86@...nel.org,
	Andi Kleen <ak@...ux.intel.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...hat.com>,
	"H. Peter Anvin" <hpa@...or.com>, Mike Travis <travis@....com>
Subject: Re: [PATCH] x86, mce: short output of MCE banks ownership information

Roland Dreier wrote:
> Seems OK, but I think it would be even more useful to find a way to
> print fewer lines of output; with CPUs that will be released shortly, a
> system with 64 or even 128 logical CPUs will not be will not be that
> exotic, and producing 128 lines of kernel log output for debugging
> information that is rarely used and where the same info can be expressed
> in 2 or 3 lines is silly-looking (and very annoying on a 57600 bps
> serial console!).

Thanks for your review!

I think we could some effort like this for other messages during
CPU initialization.

For example I googled a full dmesg of recent hardware:
  http://www.gossamer-threads.com/lists/linux/kernel/1134265
It shows that the lines like:
   :
  Booting processor 1 APIC 0x2 ip 0x6000
  Initializing CPU#1 
  Calibrating delay using timer specific routine.. 5344.67 BogoMIPS (lpj=2672337) 
  CPU: Physical Processor ID: 0 
  CPU: Processor Core ID: 1 
  CPU: L1 I cache: 32K, L1 D cache: 32K 
  CPU: L2 cache: 256K 
  CPU: L3 cache: 8192K 
  mce: CPU supports 9 MCE banks 
  CPU1: Thermal monitoring enabled (TM1) 
  CPU 1 MCA banks CMCI:2 CMCI:3 CMCI:5 SHD:6 SHD:8 
  x86 PAT enabled: cpu 1, old 0x7040600070406, new 0x7010600070106 
  CPU1: Intel(R) Core(TM) i7 CPU 920 @ 2.67GHz stepping 04 
  Skipping synchronization checks as TSC is reliable. 
   :
are that printed for every cpu.

We already eliminated "mce: CPU supports X MCE banks" in this repeat
and now going to compress "CPU X MCA banks ..." line.

I suppose:
  - Cache information can be compressed too, could be in one line.
  - Usually model name (and also cache size) will be same on all cpu.

I can understand that it is better to avoid printing same lines
again and again.  But there are more redundant messages...

Maybe there would be more desirable ways, but I think that
"compress messages shorter to bear heavy repeating" will be
a good way at this time.

Thanks,
H.Seto
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