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Date:	Mon, 9 Nov 2009 21:23:33 +0000
From: (Lennart Sorensen)
To:	"H. Peter Anvin" <>
Cc:	Lennart Sorensen <>,
	Matteo Croce <>,
	Ingo Molnar <>,
Subject: Re: i686 quirk for AMD Geode

On Mon, Nov 09, 2009 at 01:17:08PM -0800, H. Peter Anvin wrote:
> On 11/09/2009 12:16 PM, Lennart Sorensen wrote:
> > 
> > The Geode LX is what is being discussed which is in fact mostly a K6 as
> > far as I understand things.  It seems to like i686 code, other than
> > apparently those NOP instructions.  I wonder if the K6 has those noop
> > instructions and if not, perhaps gcc 4.4's -march=k6-3 would be the
> > right choice.  I have always suspected the LX was really a K6-3 based
> > design (the cache sizes are a bit different, but clock speeds and
> > instruction sets seem to match).
> > 
> > The Geode NX (which no one has mentioned yet) is an Athlon derived chip.
> > 
> *As far as I know* K6 didn't have NOPL, whereas K7 does.

Which would be mroe indication that the Geode LX may in fact be a K6
based CPU design.  The Geode NX is very clearly an Athlon (K7) and AMD
has never even tried to hide that.  They have never said what the LX is
based on, other than it isn't based on the GX (fortunately, that thing
was a buggy piece of crap).

> Someone who has access to these chips could run that as an experiment.

I have lots of Geode SC1200 (GX2 SoC) and Geode LX systems around.
I think I might even have a K6-2 at home in the garage come to think
of it.

Len Sorensen
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