| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <4B02EE1D.6020302@sgi.com>
Date: Tue, 17 Nov 2009 10:40:29 -0800
From: Mike Travis <travis@....com>
To: Hidetoshi Seto <seto.hidetoshi@...fujitsu.com>,
Ingo Molnar <mingo@...e.hu>
CC: Thomas Gleixner <tglx@...utronix.de>,
Andrew Morton <akpm@...ux-foundation.org>,
Heiko Carstens <heiko.carstens@...ibm.com>,
Roland Dreier <rdreier@...co.com>,
Randy Dunlap <rdunlap@...otime.net>, Tejun Heo <tj@...nel.org>,
Andi Kleen <andi@...stfloor.org>,
Greg Kroah-Hartman <gregkh@...e.de>,
Yinghai Lu <yhlu.kernel@...il.com>,
"H. Peter Anvin" <hpa@...or.com>,
David Rientjes <rientjes@...gle.com>,
Steven Rostedt <rostedt@...dmis.org>,
Rusty Russell <rusty@...tcorp.com.au>,
Jack Steiner <steiner@....com>,
Frederic Weisbecker <fweisbec@...il.com>, x86@...nel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH] x86, mce: rework output of MCE banks ownership information
Author: Hidetoshi Seto <seto.hidetoshi@...fujitsu.com>
The output of MCE banks ownership information on boot tend
to be long on new processor which has many banks:
CPU 1 MCA banks SHD:0 SHD:1 CMCI:2 CMCI:3 CMCI:5 SHD:6 SHD:7 SHD:8 SHD:9 SHD:12 SHD:13 SHD:14 SHD:15 SHD:16 SHD:17 SHD:18 SHD:19 SHD:20 SHD:21
This message can fill up the console output when the number
of cpus is large.
This patch suppress this info message on boot, and introduce
debug message in shorter format instead, like:
CPU 1 MCE banks map: ssCC PCss ssPP ssss ssss ss
where: s: shared, C: checked by cmci, P: checked by poll.
This patch still keep the info when ownership is updated.
E.g. if a cpu take over the ownership from hot-removed cpu,
both message will be shown:
CPU 1 MCE banks map updated: CMCI:6 CMCI:7 CMCI:10 CMCI:11
CPU 1 MCE banks map: ssCC PCCC ssPP ssCC ssss ss
v2:
- stop changing the level of message on update
- change the number of banks message on boot to debug level
Signed-off-by: Hidetoshi Seto <seto.hidetoshi@...fujitsu.com>
- Modified to not use pr_cont().
Signed-off-by: Mike Travis <travis@....com>
---
arch/x86/kernel/cpu/mcheck/mce.c | 6 +--
arch/x86/kernel/cpu/mcheck/mce_intel.c | 63 +++++++++++++++++++++++++++------
2 files changed, 55 insertions(+), 14 deletions(-)
--- linux.orig/arch/x86/kernel/cpu/mcheck/mce.c
+++ linux/arch/x86/kernel/cpu/mcheck/mce.c
@@ -1215,11 +1215,11 @@
b = cap & MCG_BANKCNT_MASK;
if (!banks)
- printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
+ pr_debug("mce: CPU supports %d MCE banks\n", b);
if (b > MAX_NR_BANKS) {
- printk(KERN_WARNING
- "MCE: Using only %u machine check banks out of %u\n",
+ pr_warning(
+ "MCE: Using only %u machine check banks out of %u\n",
MAX_NR_BANKS, b);
b = MAX_NR_BANKS;
}
--- linux.orig/arch/x86/kernel/cpu/mcheck/mce_intel.c
+++ linux/arch/x86/kernel/cpu/mcheck/mce_intel.c
@@ -64,14 +64,50 @@
mce_notify_irq();
}
-static void print_update(char *type, int *hdr, int num)
+#define MCE_MSG_LEN 120
+
+#ifdef DEBUG_KERNEL
+static void print_banks_map(int banks, char *buf)
+{
+ int i, n;
+
+ n = snprintf(buf, MCE_MSG_LEN, "CPU %d MCE banks map:",
+ smp_processor_id());
+ for (i = 0; i < banks; i++) {
+ n += snprintf(&buf[n], MCE_MSG_LEN - n,
+ "%s%s", (i % 4) ? "" : " ",
+ test_bit(i, __get_cpu_var(mce_banks_owned)) ? "C" :
+ test_bit(i, __get_cpu_var(mce_poll_banks)) ? "P" : "s");
+ }
+
+ /* (indicate if message buffer overflowed) */
+ pr_debug("%s%s\n", buf, n < MCE_MSG_LEN ? "" : "..." );
+}
+
+static void print_update(char *type, int *hdr, int num, char *buf)
+{
+ int n = *hdr;
+
+ if (n == 0)
+ n = snprintf(buf, MCE_MSG_LEN,
+ "CPU %d MCE banks map updated:", smp_processor_id());
+
+ n += snprintf(&buf[n], MCE_MSG_LEN - n, " %s:%d", type, num);
+ *hdr = n;
+}
+
+#else /* !DEBUG_KERNEL */
+
+static inline void print_banks_map(int banks, char *buf)
+{
+}
+
+static inline void print_update(char *type, int *hdr, int num, char *buf)
{
- if (*hdr == 0)
- printk(KERN_INFO "CPU %d MCA banks", smp_processor_id());
- *hdr = 1;
- printk(KERN_CONT " %s:%d", type, num);
}
+#endif
+
/*
* Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks
* on this CPU. Use the algorithm recommended in the SDM to discover shared
@@ -83,8 +119,10 @@
unsigned long flags;
int hdr = 0;
int i;
+ char buf[MCE_MSG_LEN];
spin_lock_irqsave(&cmci_discover_lock, flags);
+
for (i = 0; i < banks; i++) {
u64 val;
@@ -95,8 +133,8 @@
/* Already owned by someone else? */
if (val & CMCI_EN) {
- if (test_and_clear_bit(i, owned) || boot)
- print_update("SHD", &hdr, i);
+ if (test_and_clear_bit(i, owned) && !boot)
+ print_update("SHD", &hdr, i, buf);
__clear_bit(i, __get_cpu_var(mce_poll_banks));
continue;
}
@@ -107,16 +145,19 @@
/* Did the enable bit stick? -- the bank supports CMCI */
if (val & CMCI_EN) {
- if (!test_and_set_bit(i, owned) || boot)
- print_update("CMCI", &hdr, i);
+ if (!test_and_set_bit(i, owned) && !boot)
+ print_update("CMCI", &hdr, i, buf);
__clear_bit(i, __get_cpu_var(mce_poll_banks));
} else {
WARN_ON(!test_bit(i, __get_cpu_var(mce_poll_banks)));
}
}
- spin_unlock_irqrestore(&cmci_discover_lock, flags);
if (hdr)
- printk(KERN_CONT "\n");
+ pr_debug("%s%s\n", buf, hdr < MCE_MSG_LEN ? "" : "...");
+ if (hdr || boot)
+ print_banks_map(banks, buf);
+
+ spin_unlock_irqrestore(&cmci_discover_lock, flags);
}
/*
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Powered by blists - more mailing lists