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Message-ID: <87my2i4czt.fsf@basil.nowhere.org>
Date:	Thu, 19 Nov 2009 18:53:58 +0100
From:	Andi Kleen <andi@...stfloor.org>
To:	Nick Piggin <npiggin@...e.de>
Cc:	Arjan van de Ven <arjan@...radead.org>,
	Ingo Molnar <mingo@...e.hu>, Jan Beulich <JBeulich@...ell.com>,
	tglx@...utronix.de, linux-kernel@...r.kernel.org, hpa@...or.com,
	Ravikiran Thirumalai <kiran@...lex86.org>,
	Shai Fultheim <shai@...lemp.com>
Subject: Re: [PATCH] x86: eliminate redundant/contradicting cache line size config options

Nick Piggin <npiggin@...e.de> writes:
>
> AFAIKS, in any case that 128 byte alignment is used, cache footprint
> should not increased on a 64B line system, over 64 byte alignment.

Yes.

It's probably some silly bug somewhere. I don't think we should
completely abandon P4 systems (of which there are still plenty around)
just for silly bugs, that can be probably properly fixed.

-Andi

-- 
ak@...ux.intel.com -- Speaking for myself only.
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