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Message-ID: <20091124094421.GA3468@in.ibm.com>
Date: Tue, 24 Nov 2009 15:14:21 +0530
From: "K.Prasad" <prasad@...ux.vnet.ibm.com>
To: Frederic Weisbecker <fweisbec@...il.com>,
Ingo Molnar <mingo@...e.hu>
Cc: LKML <linux-kernel@...r.kernel.org>,
Li Zefan <lizf@...fujitsu.com>,
Alan Stern <stern@...land.harvard.edu>,
Peter Zijlstra <peterz@...radead.org>,
Arnaldo Carvalho de Melo <acme@...hat.com>,
Steven Rostedt <rostedt@...dmis.org>,
Jan Kiszka <jan.kiszka@....de>,
Jiri Slaby <jirislaby@...il.com>, Avi Kivity <avi@...hat.com>,
Paul Mackerras <paulus@...ba.org>,
Mike Galbraith <efault@....de>,
Masami Hiramatsu <mhiramat@...hat.com>,
Paul Mundt <lethal@...ux-sh.org>,
Arjan van de Ven <arjan@...ux.intel.com>
Subject: Re: [GIT PULL v6] hw-breakpoints: Rewrite on top of perf events v6
On Sun, Nov 08, 2009 at 04:28:54PM +0100, Frederic Weisbecker wrote:
> Ingo,
>
> Please pull the tracing/hw-breakpoints branch that can be found at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/frederic/random-tracing.git
> tracing/hw-breakpoints
>
Hi Frederic, Ingo,
Here are a few concerns (roughly in decreasing order of
priority) about the perf-events integrated hw-breakpoint feature.
- Freeze the breakpoint interfaces: Owing to the many current/potential
users of hw-breakpoint feature it is important to provide a stable
interface to the end-user. Changes underneath the interface can be done
in due course in a manner that does not affect the end-user's behaviour
or function signature. The present breakpoint interface requires
parameters that are best embedded in a structure for extensibility.
- Proposed migration of register allocation logic to arch-specific files
from kernel/hw_breakpoint.c. This is best done early to help easy
porting of code to other architectures (we have an active interest in
bringing support for PPC64 and S390). If done later, it will entail
additional effort in porting for each architecture.
- Fix ptrace bugs that potentially alter the semantics of ptrace.
- Bring either true system_wide support or atleast workaround the
side-effects of iterative per-cpu registration using single atomic
enablement of all per-cpu breakpoints. This can avoid stray exceptions
which would get delivered to the end-user even for failed breakpoint
requests.
Thanks,
K.Prasad
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