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Message-ID: <4B0ECD27.7050302@ru.mvista.com>
Date: Thu, 26 Nov 2009 21:47:03 +0300
From: Sergei Shtylyov <sshtylyov@...mvista.com>
To: Bartlomiej Zolnierkiewicz <bzolnier@...il.com>
Cc: Alan Cox <alan@...rguk.ukuu.org.uk>, linux-ide@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] pata_it8213: MWDMA0 is unsupported
Hello, I wrote:
>>>>>>>> MWDMA0 timings cannot be met with the PIIX based controller
>>>>>>>> programming interface.
>>>>>>>> This change should be safe as this is how we have been doing
>>>>>>>> things in IDE it8213 host driver for years.
>>>>>>>> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@...il.com>
>>>>>>>> ---
>>>>>>>> Verified with the documentation (similar case as with pata_efar).
>>>>>>> Uhhh, no...
>>>>>>> Too many damn drivers.
>>>>>>> Too much damn duplication.
>>>>>>> Too much damn subtle differences here and there.
>>>>>>> The hardware is probably fine for MWMDA0 when it comes to
>>>>>>> pata_{efar,it8213},
>>>>>>> it just not documented properly in the data sheet.
>>>>>> How so with pata_efar? The active/recovery bitfields are still
>>>>>> 2-bit wide, no?
>>>>> Yes but when TIMEx bit is disabled we are using XFER_PIO_SLOW timings.
>>> 600 ns cycle vs spec'ed 480 ns? Is it really worth it?
>> 960 ns actually
> That table you're looking at (probably in the SLC90E66 datasheet?)
> must be screwed up. 960 ns is used for command cycles, according to
> Intel's docs, data cycles run at 600 ns...
Well, after doublke checking 82371AB datasheet has 660 ns, and ICH PRM
has 900 ns. Not sure where I got what I've cited now, perhaps in some older
version of PRM... what a mess indeed. :-/
MBR, Sergei
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