linux-kernel - Re: [PATCH] calgary: Increase the maximum PHB bus number

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Message-ID: <61b968730912082104q7e47576am6b330ae19d732bf2@mail.gmail.com>
Date:	Tue, 8 Dec 2009 23:04:40 -0600
From:	Jon Mason <jdmason@...zu.us>
To:	djwong@...ibm.com
Cc:	Ingo Molnar <mingo@...e.hu>, discuss@...-64.org,
	Corinna Schultz <coschult@...ibm.com>,
	Muli Ben-Yehuda <muli@...ibm.com>,
	linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] calgary: Increase the maximum PHB bus number

It looks fine, but please change the comment to be similar to the
other multi-line comments in the code.  This would look like:

/*
 * The maximum PHB bus number.
 * x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
 * x3950M2: 4 chassis, 48 PHBs per chassis           = 192
 * x3950 (PCIE): 8 chassis, 32 PHBs per chassis     = 256
 * x3950 (PCIX): 8 chassis, 16 PHBs per chassis     = 128
 */

Thanks,
Jon

On Tue, Dec 8, 2009 at 6:59 PM, Darrick J. Wong <djwong@...ibm.com> wrote:
> Newer systems (x3950M2) can have 48 PHBs per chassis and 8 chassis, so bump the
> limits up and provide an explanation of the requirements for each class.
>
> Signed-off-by: Darrick J. Wong <djwong@...ibm.com>
> ---
>
>  arch/x86/kernel/pci-calgary_64.c |   13 +++++++++----
>  1 files changed, 9 insertions(+), 4 deletions(-)
>
>
> diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c
> index e6ec8a2..a693037 100644
> --- a/arch/x86/kernel/pci-calgary_64.c
> +++ b/arch/x86/kernel/pci-calgary_64.c
> @@ -102,10 +102,15 @@ int use_calgary __read_mostly = 0;
>  #define PMR_SOFTSTOPFAULT      0x40000000
>  #define PMR_HARDSTOP           0x20000000
>
> -#define MAX_NUM_OF_PHBS                8 /* how many PHBs in total? */
> -#define MAX_NUM_CHASSIS                8 /* max number of chassis */
> -/* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
> -#define MAX_PHB_BUS_NUM                (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
> +/*
> +   The maximum PHB bus number.
> +   x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
> +   x3950M2: 4 chassis, 48 PHBs per chassis        = 192
> +   x3950 (PCIE): 8 chassis, 32 PHBs per chassis   = 256
> +   x3950 (PCIX): 8 chassis, 16 PHBs per chassis   = 128
> +*/
> +#define MAX_PHB_BUS_NUM                384
> +
>  #define PHBS_PER_CALGARY       4
>
>  /* register offsets in Calgary's internal register space */
>
--
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