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Message-ID: <20091211194247.GD30407@aftab>
Date: Fri, 11 Dec 2009 20:42:47 +0100
From: Borislav Petkov <borislav.petkov@....com>
To: "H. Peter Anvin" <hpa@...or.com>, Ingo Molnar <mingo@...e.hu>,
Thomas Gleixner <tglx@...utronix.de>
CC: x86 <x86@...nel.org>, LKML <linux-kernel@...r.kernel.org>
Subject: [PATCH] x86, cache: add cache index disable attributes only on L3
caches
From: Borislav Petkov <borislav.petkov@....com>
Date: Tue, 6 Oct 2009 20:11:59 +0200
Subject: [PATCH] x86, cache: add cache index disable attributes only on L3 caches
the cache_disable_[01] attribute in
/sys/devices/system/cpu/cpu?/cache/index[0-3]/
is enabled on all cache levels although only L3 supports it. Fix it.
Signed-off-by: Borislav Petkov <borislav.petkov@....com>
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 38 ++++++++++++++++++++++----------
1 files changed, 26 insertions(+), 12 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 6c40f6b..7accaeb 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -805,16 +805,24 @@ static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
show_cache_disable_1, store_cache_disable_1);
+#define DEFAULT_SYSFS_CACHE_ATTRS \
+ &type.attr, \
+ &level.attr, \
+ &coherency_line_size.attr, \
+ &physical_line_partition.attr, \
+ &ways_of_associativity.attr, \
+ &number_of_sets.attr, \
+ &size.attr, \
+ &shared_cpu_map.attr, \
+ &shared_cpu_list.attr
+
static struct attribute *default_attrs[] = {
- &type.attr,
- &level.attr,
- &coherency_line_size.attr,
- &physical_line_partition.attr,
- &ways_of_associativity.attr,
- &number_of_sets.attr,
- &size.attr,
- &shared_cpu_map.attr,
- &shared_cpu_list.attr,
+ DEFAULT_SYSFS_CACHE_ATTRS,
+ NULL
+};
+
+static struct attribute *default_l3_attrs[] = {
+ DEFAULT_SYSFS_CACHE_ATTRS,
&cache_disable_0.attr,
&cache_disable_1.attr,
NULL
@@ -854,7 +862,6 @@ static struct sysfs_ops sysfs_ops = {
static struct kobj_type ktype_cache = {
.sysfs_ops = &sysfs_ops,
- .default_attrs = default_attrs,
};
static struct kobj_type ktype_percpu_entry = {
@@ -907,6 +914,7 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
unsigned int cpu = sys_dev->id;
unsigned long i, j;
struct _index_kobject *this_object;
+ struct _cpuid4_info *this_leaf;
int retval;
retval = cpuid4_cache_sysfs_init(cpu);
@@ -925,8 +933,14 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
this_object = INDEX_KOBJECT_PTR(cpu, i);
this_object->cpu = cpu;
this_object->index = i;
- retval = kobject_init_and_add(&(this_object->kobj),
- &ktype_cache,
+ this_leaf = CPUID4_INFO_IDX(cpu, i);
+
+ if (this_leaf->can_disable)
+ ktype_cache.default_attrs = default_l3_attrs;
+ else
+ ktype_cache.default_attrs = default_attrs;
+
+ retval = kobject_init_and_add(&(this_object->kobj), &ktype_cache,
per_cpu(cache_kobject, cpu),
"index%1lu", i);
if (unlikely(retval)) {
--
1.6.5.4
--
Regards/Gruss,
Boris.
Operating | Advanced Micro Devices GmbH
System | Karl-Hammerschmidt-Str. 34, 85609 Dornach b. München, Germany
Research | Geschäftsführer: Andrew Bowd, Thomas M. McCoy, Giuliano Meroni
Center | Sitz: Dornach, Gemeinde Aschheim, Landkreis München
(OSRC) | Registergericht München, HRB Nr. 43632
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