linux-kernel - Re: [PATCH 0/12] pci: update pci bridge resources

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Message-Id: <1261370692.26429.78.camel@dc7800.home>
Date:	Sun, 20 Dec 2009 21:44:52 -0700
From:	Bjorn Helgaas <bjorn.helgaas@...com>
To:	Yinghai Lu <yinghai@...nel.org>
Cc:	Jesse Barnes <jbarnes@...tuousgeek.org>,
	Ingo Molnar <mingo@...e.hu>,
	Linus Torvalds <torvalds@...ux-foundation.org>,
	Ivan Kokshaysky <ink@...assic.park.msu.ru>,
	Kenji Kaneshige <kaneshige.kenji@...fujitsu.com>,
	Alex Chiang <achiang@...com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>
Subject: Re: [PATCH 0/12] pci: update pci bridge resources

On Sun, 2009-12-20 at 17:42 -0800, Yinghai Lu wrote:
> Bjorn Helgaas wrote:
> > On Fri, 2009-12-18 at 12:54 -0800, Yinghai Lu wrote:
> >> this patche set is trying to update pci bridge BAR when that BAR is big enough.
> >>
> >> default it is disabled.
> >>
> >> could use pci=try=2 to enable it.
> > 
> > I think you mean "when the BAR is *not* big enough."  And strictly
> > speaking, I think you're concerned with the bridge *window*, which isn't
> > actually a bridge BAR.
> 
> in PCI bridge to bridge spec 1.1, page 38, 3.2.5.1 still call them bridge "Base Address Registers"
> 
> so should be fine we call them Bridge BAR, 
> 
> and we still have device BAR...

PCI bridges have optional BARs, described as you point out in section
3.2.5.1.  These work the same as BARs on any other PCI device, and your
patches aren't concerned with these.

Your patch series is primarily concerned with the bridge Base & Limit
registers described in sections 3.2.5.6 (I/O), 3.2.5.8 (memory), and
3.2.5.9 (prefetchable memory).  These define the address ranges
forwarded from one bridge interface to the other.  The spec doesn't have
a nice term for these ranges, but they're often referred to as "windows"
or "apertures" because they are the areas where you can "see through"
the bridge to devices on the other side.

Bjorn


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