linux-kernel - Re: [Fdutils] DMA cache consistency bug introduced in 2.6.28

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Message-ID: <87bphpd4rt.fsf@basil.nowhere.org>
Date:	Wed, 23 Dec 2009 17:38:46 +0100
From:	Andi Kleen <andi@...stfloor.org>
To:	Linus Torvalds <torvalds@...ux-foundation.org>
Cc:	Mark Hounschell <markh@...pro.net>,
	"Pallipadi, Venkatesh" <venkatesh.pallipadi@...el.com>,
	"dmarkh@....rr.com" <dmarkh@....rr.com>,
	Alain Knaff <alain@...ff.lu>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	"fdutils@...tils.linux.lu" <fdutils@...tils.linux.lu>,
	"Li, Shaohua" <shaohua.li@...el.com>, Ingo Molnar <mingo@...e.hu>
Subject: Re: [Fdutils] DMA cache consistency bug introduced in 2.6.28

Linus Torvalds <torvalds@...ux-foundation.org> writes:

> It's not using the lapic for CPU0. 
>
> Using the HPET as a per-cpu timer is some crazy sh*t, since it's pretty 
> expensive to reprogram (compared to the local apic). And having different 
> timers for different CPU's is just odd.
>
> The fact that the timer subsystem can do this and it all (mostly) works at 
> all is nice and impressive, but doesn't make it any less crazy ;)

I suspect it's a system where the APIC timer stops in deeper idle
states and it supports them. In this case CPU #0 does timer broadcasts
when needed to wake the other CPUs up from deep C, but for that it has
to run with HPET. At least the other ones can still enjoy the LAPIC
timer.

This might suggest that Mark's floppy controller doesn't like
deep C? Mark, did you try booting with processor.max_cstate=1
and HPET enabled?

-Andi
-- 
ak@...ux.intel.com -- Speaking for myself only.
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