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Message-Id: <1262649945.2700.364.camel@sbs-t61.sc.intel.com>
Date: Mon, 04 Jan 2010 16:05:44 -0800
From: Suresh Siddha <suresh.b.siddha@...el.com>
To: "H. Peter Anvin" <hpa@...or.com>
Cc: Yinghai Lu <yinghai@...nel.org>,
"Eric W. Biederman" <ebiederm@...ssion.com>,
Jesse Brandeburg <jesse.brandeburg@...il.com>,
Ingo Molnar <mingo@...e.hu>,
Thomas Gleixner <tglx@...utronix.de>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Andrew Morton <akpm@...ux-foundation.org>,
NetDEV list <netdev@...r.kernel.org>,
"Brandeburg, Jesse" <jesse.brandeburg@...el.com>
Subject: Re: Subject: [PATCH 1/2] x86: get back 15 vectors
On Mon, 2010-01-04 at 11:50 -0800, H. Peter Anvin wrote:
> On 01/04/2010 11:45 AM, Suresh Siddha wrote:
> > On Mon, 2010-01-04 at 11:35 -0800, Yinghai Lu wrote:
> >> sth like this?
> >>
> >> Subject: [PATCH 1/2] x86: get back 16 vectors
> >>
> >> -v2: according to hpa that we could start from 0x10
> >> according to Eric, we should hold 16 vectors for IRQ MOVE
> >>
> >> Signed-off-by: Yinghai Lu <yinghai@...nel.org>
> >>
> >
> > Yinghai we have to change IRQ_MOVE_CLEANUP_VECTOR to 0x1f or so. From
> > the cpu perspective this vector is documented as illegal, so we need to
> > check if this change will work on the cpu's we have today to get some
> > confidence.
> >
>
> It's documented as reserved, not illegal. The ability for the APIC to
> generate vectors starting at 0x10 is documented, as is the ability for
> the CPU to receive any vector number as an interrupt -- in fact, the
> legacy BIOS relies on being able to receive interrupts starting at
> vector 0x08. It causes problems galore, but only at the software level.
I have checked out couple of platforms (including 32-bit atom) and 0x1f
vector logic seems to be working.
Hopefully we won't have other hardware or software issues (vmm
restrictions etc) with this logic.
thanks,
suresh
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