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Message-ID: <4B45803D.106@kernel.org> Date: Wed, 06 Jan 2010 22:33:33 -0800 From: Yinghai Lu <yinghai@...nel.org> To: Torsten Kaiser <just.for.lkml@...glemail.com> CC: Robert Hancock <hancockrwd@...il.com>, Linux Kernel Mailing List <linux-kernel@...r.kernel.org>, Vivek Mahajan <vivek.mahajan@...escale.com>, Jeff Garzik <jgarzik@...ox.com>, linux-ide@...r.kernel.org, Peer Chen <pchen@...dia.com> Subject: Re: New MSI support in sata_sil24 still broken in 2.6.33-rc3 On 01/06/2010 07:28 PM, Torsten Kaiser wrote: > On Thu, Jan 7, 2010 at 4:05 AM, Robert Hancock <hancockrwd@...il.com> wrote: >> Hmm, well presumably the problem isn't related to that then. I was looking >> at your lspci output though: >> >> 00:05.0 IDE interface: nVidia Corporation MCP55 SATA Controller (rev a3) >> (prog-if 85 [Master SecO PriO]) >> Subsystem: ASUSTeK Computer Inc. Device 81f0 >> Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- >> Stepping- SERR- FastB2B- DisINTx+ >> Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- >> <TAbort- <MAbort- >SERR- <PERR- INTx- >> Latency: 0 (750ns min, 250ns max) >> Interrupt: pin A routed to IRQ 30 >> Region 0: I/O ports at cc00 [size=8] >> Region 1: I/O ports at c880 [size=4] >> Region 2: I/O ports at c800 [size=8] >> Region 3: I/O ports at c480 [size=4] >> Region 4: I/O ports at c400 [size=16] >> Region 5: Memory at efafb000 (32-bit, non-prefetchable) [size=4K] >> Capabilities: [44] Power Management version 2 >> Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA >> PME(D0-,D1-,D2-,D3hot-,D3cold-) >> Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- >> Capabilities: [b0] MSI: Enable+ Count=1/4 Maskable- 64bit+ >> Address: 00000000fee0f00c Data: 4189 >> Capabilities: [cc] HyperTransport: MSI Mapping Enable- Fixed+ >> >> The HT MSI Mapping capability is not enabled on the device. I'm thinking it >> should be, but I'm not sure. And it's also not enabled on the bus which has >> the Silicon Image controller: >> >> 04:00.0 Mass storage controller: Silicon Image, Inc. SiI 3132 Serial ATA >> Raid II Controller (rev 01) >> >> on its subordinate bus: >> >> 00:0b.0 PCI bridge: nVidia Corporation MCP55 PCI Express bridge (rev a3) >> (prog-if 00 [Normal decode]) >> Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- >> Stepping- SERR- FastB2B- DisINTx+ >> Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- >> <TAbort- <MAbort- >SERR- <PERR- INTx- >> Latency: 0, Cache Line Size: 64 bytes >> Bus: primary=00, secondary=04, subordinate=04, sec-latency=0 >> I/O behind bridge: 0000e000-0000efff >> Memory behind bridge: efe00000-efefffff >> Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- >> <TAbort- <MAbort- <SERR- <PERR- >> BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- >> PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- >> Capabilities: [40] Subsystem: nVidia Corporation Device 0000 >> Capabilities: [48] Power Management version 2 >> Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA >> PME(D0+,D1+,D2+,D3hot+,D3cold+) >> Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- >> Capabilities: [50] MSI: Enable+ Count=1/2 Maskable- 64bit+ >> Address: 00000000fee0f00c Data: 4149 >> Capabilities: [60] HyperTransport: MSI Mapping Enable- Fixed- >> Mapping Address Base: 00000000fee00000 >> >> CCing some people that might have some idea about this.. > > part of the PCI tree: > +-0b.0-[04]----00.0 Silicon Image, Inc. SiI 3132 Serial > ATA Raid II Controller > +-0c.0-[03]----00.0 Broadcom Corporation NetXtreme BCM5754 > Gigabit Ethernet PCI Express > +-0d.0-[02]----00.0 Broadcom Corporation NetXtreme BCM5754 > Gigabit Ethernet PCI Express > +-0f.0-[01]--+-00.0 ATI Technologies Inc RV370 5B60 > [Radeon X300 (PCIE)] > | \-00.1 ATI Technologies Inc RV370 [Radeon X300SE] > > The three devices attached to 0c.0, 0d.0 and 0f.0 work correctly with MSI. > But each of these PCI Express bridges also has this Mapping disabled: > Capabilities: [60] HyperTransport: MSI Mapping Enable- Fixed- > Mapping Address Base: 00000000fee00000 so that could be Sil silicon problem or driver problem. > > This capability seems only to be enabled at the root: > 00:00.0 RAM memory: nVidia Corporation MCP55 Memory Controller (rev a2) > Subsystem: ASUSTeK Computer Inc. Device 81f0 > Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- > ParErr- Stepping- S > Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- > <TAbort- <MAbort > Latency: 0 > Capabilities: [44] HyperTransport: Slave or Primary Interface > Command: BaseUnitID=0 UnitCnt=15 MastHost- DefDir- DUL- > Link Control 0: CFlE+ CST- CFE- <LkFail- Init+ EOC- > TXO- <CRCErr=0 Isoc > Link Config 0: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- > LWI=16bit DwFcInE > Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ > TXO+ <CRCErr=0 Isoc > Link Config 1: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- > LWI=8bit DwFcInEn- > Revision ID: 1.03 > Link Frequency 0: 1.0GHz > Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- > Link Frequency Capability 0: 200MHz+ 300MHz+ 400MHz+ > 500MHz+ 600MHz+ 80 > Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- > Link Frequency 1: 200MHz > Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- > Link Frequency Capability 1: 200MHz- 300MHz- 400MHz- > 500MHz- 600MHz- 80 > Error Handling: PFlE+ OFlE+ PFE- OFE- EOCFE- RFE- > CRCFE- SERRFE- CF- RE > Prefetchable memory behind bridge Upper: 00-00 > Bus Number: 00 > Capabilities: [dc] HyperTransport: MSI Mapping Enable+ Fixed- > Mapping Address Base: 00000000fee00000 > >>>From my dmesg: > [ 1.636318] pci 0000:00:00.0: Found enabled HT MSI Mapping > [ 1.641854] pci 0000:00:00.0: Found enabled HT MSI Mapping > [ 1.647420] pci 0000:00:00.0: Found enabled HT MSI Mapping > [ 1.652946] pci 0000:00:00.0: Found enabled HT MSI Mapping > [ 1.658505] pci 0000:00:00.0: Found enabled HT MSI Mapping > [ 1.664055] pci 0000:00:00.0: Found enabled HT MSI Mapping > [ 1.669597] pci 0000:00:00.0: Found enabled HT MSI Mapping > [ 1.675172] pci 0000:00:00.0: Found enabled HT MSI Mapping > [ 1.680715] pci 0000:00:00.0: Found enabled HT MSI Mapping > > I found this output very strange, as it always referred to the same > pci device, but looking at the code, that might only be a visual nit. > > The output is from msi_ht_cap_enabled() in drivers/pci/quirks.c. This > will be called via nv_ht_enable_msi_mapping(), but always to check the > 'host_bridge', not the devices that __nv_msi_ht_cap_quirk() loops > over. if the host_brige get that ht_msi mapping enabled, then don't need to enable that on bridge under that. YH -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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