linux-kernel - Re: drm/radeon/kms: fix up LVDS handling on macs (v2)

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Message-ID: <1263437142.724.320.camel@pasglop>
Date:	Thu, 14 Jan 2010 13:45:42 +1100
From:	Benjamin Herrenschmidt <benh@...nel.crashing.org>
To:	Alex Deucher <alexdeucher@...il.com>
Cc:	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	Dave Airlie <airlied@...hat.com>,
	Michel Dänzer <michel@...nzer.net>
Subject: Re: drm/radeon/kms: fix up LVDS handling on macs (v2)

On Thu, 2010-01-14 at 00:59 +0000, Linux Kernel Mailing List wrote:
> Gitweb:     http://git.kernel.org/linus/3890ddf56dbc0f804953198e65a7e406ed654576
> Commit:     3890ddf56dbc0f804953198e65a7e406ed654576
> Parent:     804c7559e9376c3ba78ae15a30337b1e24f8ae80
> Author:     Alex Deucher <alexdeucher@...il.com>
> AuthorDate: Tue Jan 12 11:16:57 2010 -0500
> Committer:  Dave Airlie <airlied@...hat.com>
> CommitDate: Wed Jan 13 13:25:08 2010 +1000
> 
>     drm/radeon/kms: fix up LVDS handling on macs (v2)
>     
>     Based on radeonfb code and recent ddx fix.
>     
>     v2: minor formatting fix from Michel Dänzer
>     
>     Signed-off-by: Alex Deucher <alexdeucher@...il.com>
>     Reviewed-by: Michel Dänzer <michel@...nzer.net>
>     Tested-by: Michel Dänzer <michel@...nzer.net>
>     Signed-off-by: Dave Airlie <airlied@...hat.com>

I have to dbl check that ... but I think the "Real" issue is that some
panel have inverted polarity on the PWM signal. Thus if BLON is turned
off the panels goes full backlight instead among other things :-)

However, not all macs are the same. If you look at the radeonfb code,
we do things differently depending on the mac model...

I don't know if there's a "proper" way to figure out how the panel is
really wired on these. Here, the ATI "mac" guys might be able to help
by telling us how the Mac driver figures it out :-)

Cheers,
Ben.

> ---
>  drivers/gpu/drm/radeon/radeon_legacy_encoders.c |   21 ++++++++++++++++++++-
>  1 files changed, 20 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
> index 981508f..38e45e2 100644
> --- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
> +++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
> @@ -46,6 +46,7 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
>  	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
>  	uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
>  	int panel_pwr_delay = 2000;
> +	bool is_mac = false;
>  	DRM_DEBUG("\n");
>  
>  	if (radeon_encoder->enc_priv) {
> @@ -58,6 +59,15 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
>  		}
>  	}
>  
> +	/* macs (and possibly some x86 oem systems?) wire up LVDS strangely
> +	 * Taken from radeonfb.
> +	 */
> +	if ((rdev->mode_info.connector_table == CT_IBOOK) ||
> +	    (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) ||
> +	    (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) ||
> +	    (rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
> +		is_mac = true;
> +
>  	switch (mode) {
>  	case DRM_MODE_DPMS_ON:
>  		disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
> @@ -74,6 +84,8 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
>  
>  		lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
>  		lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON);
> +		if (is_mac)
> +			lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
>  		lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
>  		udelay(panel_pwr_delay * 1000);
>  		WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
> @@ -85,7 +97,14 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
>  		WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
>  		lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
>  		lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
> -		lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
> +		if (is_mac) {
> +			lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
> +			WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
> +			lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
> +		} else {
> +			WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
> +			lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
> +		}
>  		udelay(panel_pwr_delay * 1000);
>  		WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
>  		WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
> --
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